Abstract: Disclosed are compounds which inhibit the activity of anti-apoptotic Bcl-2 proteins, compositions containing the compounds and methods of treating diseases during which is expressed anti-apoptotic Bcl-2 protein.

Abstract: Disclosed are compounds which inhibit the activity of anti-apoptotic Bcl-2 proteins, compositions containing the compounds and methods of treating diseases during which is expressed anti-apoptotic Bcl-2 protein.

Abstract: Disclosed are compounds which inhibit the activity of anti-apoptotic Bcl-2 proteins, compositions containing the compounds and methods of treating diseases during which is expressed anti-apoptotic Bcl-2 protein.

Abstract: The present invention discloses an integrated analysis device for simultaneously detecting exhaled breath condensates (EBCs) and volatile organic compounds (VOCs) in human exhaled breath. The device comprises a module for sampling, separating and enriching a detected object, an EBCs detection module and a combined VOCs detection module. The module for sampling, separating and enriching a detected object is connected with the EBCs detection module via a syringe pump for sample injection. The module for sampling, separating and enriching a detected object is connected with the combined VOCs detection module by a capillary separation column. In the present invention, it is achieved that EBCs and VOCs in human exhaled breath are simultaneously sampled, separated and condensed; the heavy metal ions, cell factors, etc.

Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region,

Abstract: Compounds which inhibit the activity of anti-apoptotic Mcl-1 protein, compositions containing the compounds, and methods of treating diseases involving overexpressed or unregulated Mcl-1 protein are disclosed.

Abstract: A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel.

Abstract: A method for fabricating a small-scale MOS device, including: preparing a substrate; forming a first trench in the substrate along a first side of the gate region and forming a second trench in the substrate along a second side of the gate region, the first side of the gate region opposite the second side of the gate region; forming a first lightly doped drain region and a second lightly doped drain region in the first trench and the second trench, respectively; forming a third trench in the substrate overlapping at least a first portion of the first lightly doped drain region and a fourth trench in the substrate overlapping at least a first portion of the second lightly doped drain region; and forming a source region and a drain region in the third trench and the fourth trench, respectively.

Abstract: A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region.

Abstract: A computer-implemented method is disclosed for speeding up database access of electronic design automation (EDA) tool which utilizes a database manager for file access. The EDA tool accesses a plurality of design files, and each of the plurality of design files is associated with one of a plurality of design units for an integrated circuit (IC). The plurality of design files are encapsulated into an archive file which comprises a plurality of data units, wherein each of the data units corresponds to a design file. A request to access a design file will be redirected to access the archive file. The design file is then accessed by accessing the corresponding data unit in the archive file.

Abstract: A method for fabricating VDMOS devices includes providing a semiconductor substrate; forming a first N-type epitaxial layer on the semiconductor substrate; forming a hard mask layer with an opening on the first N-type epitaxial layer; etching the first N-type epitaxial layer along the opening until the semiconductor substrate is exposed, to form P-type barrier figures; forming a P-type barrier layer in the P-type barrier figures, the P-type barrier layer having a same thickness as that of the first N-type epitaxial layer; removing the hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate on the second N-type epitaxial layer; forming a source in the second N-type epitaxial layer on both side of the gate; and forming a drain on the back of the semiconductor substrate relative to the gate and the source.

Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

Abstract: The present invention provides new polyimide materials suitable for use in optically transparent fiber composites, ribbon composites, and optical communications applications. The polyimide compounds include monomeric repeat units comprising a fluorinated moiety and a fluorene cardo structure. The polyimides exhibit good optical transparency and have a low absolute thermo-optic coefficient (|dn/dT|).

Abstract: A method for manufacturing compatible vertical double diffused metal oxide semiconductor (VDMOS) transistor and lateral double diffused metal oxide semiconductor (LDMOS) transistor includes: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; forming an N-buried region in the substrate; forming an epitaxial layer on the N-buried layer region; forming isolation regions in the LDMOS transistor region and the VDMOS transistor region; forming a drift region in the LDMOS transistor region; forming gates in the LDMOS transistor region and the VDMOS transistor region; forming PBODY regions in the LDMOS transistor region and the VDMOS transistor region; forming an N-type GRADE region in the LDMOS transistor region; forming an NSINK region in the VDMOS transistor region, where the NSINK region is in contact with the N-buried layer region; forming sources and drains in the LDMOS transistor region and the VDMOS transistor region; and forming a P+ region in the LDMOS transistor region,

Abstract: In one aspect, the present invention provides for a compound of Formula I in which the variable X1a, X1b, X1c, X1d, Q, A, R1, B, L, E, and the subscripts m and n have the meanings as described herein. In another aspect, the present invention provides for pharmaceutical compositions comprising compounds of Formula I as well as methods for using compounds of Formula I for the treatment of diseases and conditions (e.g., cancer, thrombocythemia, etc) characterized by the expression or over-expression of Bcl-2 anti-apoptotic proteins, e.g., of anti-apoptotic Bcl-xL proteins.

Abstract: Disclosed are compounds which inhibit the activity of anti-apoptotic Bcl-2 proteins, compositions containing the compounds and methods of treating diseases during which is expressed anti-apoptotic Bcl-2 protein.

Abstract: A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist la

Abstract: Compounds of formula I wherein A1, A2, and A3 are as defined herein are inhibitors of PIM kinase. The compounds of formula I are useful for the treatment of diseases such as cancer.

Abstract: Methods of forming microelectronic structures using multilayer processes are disclosed. The methods comprise the use of a developer-soluble protective layer adjacent the substrate surface in a multilayer stack to protect the substrate during pattern transfer. After etching, the pattern is transferred into the developer-soluble protective layer using a developer instead of etching required by previous methods. Conventional developer-soluble anti-reflective coatings and gap-fill materials can be used to form the protective layer. Custom layers with developer solubility can also be prepared. Microelectronic structures formed by the above processes are also disclosed.

Abstract: Compounds of formula (I) where X1, C1, and D1 are defined herein, are inhibitors of polo-like kinases. The compounds of formula (I) are useful for treatment of diseases of cellular proliferation, such as, for example, cancer.