Abstract: A method for wireless communication at a user equipment (UE) and related apparatus are provided. In the method, the UE identifies the cell type of a cell based on the support for the UE operating with reduced capability. The cell type may be the reduced-capability (RC) type, indicating the support for the UE operating with the reduced capability, the fallback (FB) type, indicating a lack of support for the UE operating with the reduced capability and support for establishing a connection with the UE operating with the reduced capability, and the neither (N) type, indicating the lack of support for the UE operating with the reduced capability and a lack of support for establishing a connection with the UE operating with the reduced capability. The UE further manages a connection between the UE and the cell based on the cell type.

Abstract: A method for forming an interconnection structure includes depositing a dielectric layer over a first interconnect layer, wherein the first interconnect layer comprises a first metallization layer; forming a via opening in the dielectric layer, and forming a conductive via in the via opening. Forming the via opening includes: etching a recess in the dielectric layer above the first metallization layer; etching a first lateral recess in the dielectric layer at a sidewall of the recess; and after etching the first lateral recess, etching the recess downward to expose the first metallization layer.

Abstract: The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). According to an embodiment, a method performed by a UE is provided. The method comprises transmitting, to an access and mobility management function (AMF), information indicating that the UE supports network slice replacement feature, and in case that there is a protocol data unit (PDU) session associated with a single network slice selection assistance information (S-NSSAI) that needs to be replaced, receiving, from the AMF, a mapping of the S-NSSAI to an alternative S-NSSAI.

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip may include an upper bonding pad, an upper test pad, and an upper dielectric layer that surrounds the upper bonding pad and the upper test pad. The second semiconductor chip includes a lower bonding pad in contact with the upper bonding pad, a lower test pad in contact with the upper test pad, and a lower dielectric layer that surrounds the lower bonding pad and the lower test pad.

Abstract: A method according to an embodiment of the present invention corresponds to a method for transmitting, by a gateway, a synchronization signal block (SSB) through a plurality of satellites, and may comprise the steps of: determining satellite identification SSBs for identifying a plurality of satellites, respectively; determining beam identification SSBs for identifying beams usable for the plurality of satellites, respectively; and controlling the satellite identification SSBs and the beam identification SSBs to be transmitted to the plurality of satellites, respectively, through a predetermined resource, wherein the satellite identification SSBs and each of the beam identification SSBs have different SSB indices from each other.

Abstract: A semiconductor package film includes a base film having sprocket holes arranged in a first direction in an edge area at a periphery of a main area. The edge area is adjacent to the main area in a second direction intersecting the first direction. The semiconductor package film includes a circuit line disposed in the main area, and a support member disposed on the base film, the support member being adjacent to the sprocket holes in the edge area. The support member includes a support extending in the first direction, and protective walls connected to the support. The protective walls are spaced apart from each other with the sprocket holes disposed between the protective walls.

Abstract: A method of a terminal may comprise: receiving on-demand synchronization signal block (SSB) transmission configuration information from a first base station to which the terminal is connected; and receiving an on-demand SSB from a second base station based on the on-demand SSB transmission configuration information, wherein the on-demand SSB transmission configuration information includes at least one of capability information of the second base station, on-demand SSB resource information, a number of on-demand SSB transmissions, on-demand SSB transmission indication, or channel state information (CSI) configuration information.

Abstract: A semiconductor package according to an embodiment includes a first insulating layer including a cavity; a connection member buried in the cavity of the first insulating layer; and a molding layer buried in the cavity and surrounding the connection member, wherein a width of the molding layer gradually decreases along a direction from a lower surface of the first insulating layer to an upper surface of the first insulating layer.

Abstract: An operation method of a wireless communication device includes receiving a first signal including a first reference signal group, calculating a first residual frequency offset based on the first signal, receiving a second signal that is subsequent to the first signal and includes a second reference signal group, compensating a phase of the second signal based on the first residual frequency offset, estimating a first channel based on first channel characteristics, the first reference signal group, and the first signal, estimating a second channel based on second channel characteristics, the second reference signal group, and the second signal of which the phase is compensated, and calculating a second residual frequency offset based on the first channel estimation and the second channel estimation.

Abstract: A light-emitting diode includes: a substrate, an epitaxial layer and a protective layer; the epitaxial layer is disposed on the substrate and includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially in that order; the protective layer covers the epitaxial layer; the epitaxial layer is divided into chiplets, each chiplet includes transverse and longitudinal sidewalls intersecting in transverse and longitudinal directions, dicing channels are defined between adjacent chiplets, the dicing channels include transverse and longitudinal dicing channels extending respectively in the transverse and longitudinal directions, the protective layer covers the dicing channels and chiplet sidewalls, a patterned structure is disposed on the protective layer in an intersecting area of the transverse and the longitudinal dicing channels, and includes a groove extending toward the substrate.

Abstract: Disclosed are a compound for an organic optoelectronic device represented by Chemical Formula 1, a composition for an organic optoelectronic device including the same, an organic optoelectronic device, and a display device. Details for Chemical Formula 1 are the same as described in the specification.

Abstract: A memory chip includes a plurality of micro pattern lines, a capping layer covering portions of the micro pattern lines. A bonding pad penetrates the capping layer and is coupled to one of the micro pattern lines. The bonding pad includes a first pad portion coupled to the associated micro pattern line and a second pad portion coupled to the first pad portion and exposed to a top surface of the memory chip. An upper surface of the second pad portion has a convex shape.

Abstract: Provided is a ReBCO-based high-temperature superconductor composition and a method of preparing the same comprising substituting a part of Gd with Ho, wherein the ReBCO-based high-temperature superconductor is represented by ReBa2Cu3O7-?, in which Re comprises or consists of Gd and Ho. The superconductor may improve the critical current density without a change in the critical temperature.

Abstract: A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack, a pass gate overlapping a contact region of the gate stack and opening a cell array region of the gate stack, a doped semiconductor layer spaced apart from the pass gate and overlapping the cell array region of the gate stack, and an active pillar passing through the pass gate.

Abstract: An artificial intelligence device includes a memory in which a structural formula image is stored, and a processor configured to obtain information on a plurality of atomic regions from the structural formula image, to obtain information on bonding relationships between a plurality of atoms on the basis of the information on the plurality of atomic regions, to generate an adjacency matrix on the basis of the information on the plurality of atomic regions and the information on bonding relationships between the plurality of atoms, and to generate a predetermined string format corresponding to the structural formula image on the basis of the adjacency matrix.

Abstract: A semiconductor device may include a gate structure including gate lines and insulating layers that are alternately stacked; a channel structure extending through the gate structure; a dummy gate structure including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; and an isolation insulating structure including horizontal portions stacked between the gate structure and the dummy gate structure and vertical portions extending through the horizontal portions.

Abstract: Disclosed is a privacy-preserving electrocardiogram (ECG) data collecting method for arrhythmia classification. The privacy-preserving ECG data collecting method is performed by a computing device including at least a processor and includes training a feature extraction model, a personal identification model, and an arrhythmia classification model using learning data that includes ECG data with a predetermined length; and training a noise model, and the feature extraction model receives the ECG data as input and outputs ECG features, the personal identification model receives the ECG features as input and identifies an individual corresponding to the ECG features, the arrhythmia classification model receives the ECG features as input and classifies arrhythmia corresponding to the ECG features, and the noise model generates noise with the same length as that of the ECG features.

Abstract: A semiconductor device may include a first semiconductor structure including a substrate, an active region in the substrate, a device isolation region defining the active region, and a capacitor structure on the device isolation region and vertically overlapping the device isolation region. The capacitor structure may include a first electrode structure extending in a first direction and including first capacitor electrodes stacked in the first direction, a second electrode structure including second capacitor electrodes stacked in the first direction, and a first insulating structure between the first electrode structure and the second electrode structure. Each of the first capacitor electrodes and the second capacitor electrodes are alternately arranged and spaced apart from each other in a second direction parallel to an upper surface of the substrate, extend in a third direction perpendicular to the first direction and the second direction, and has a plate shape.

Abstract: A method for predicting and reducing a risk of acute kidney injury (AKI) after non-cardiac surgery includes selecting factors associated with an occurrence of acute kidney injury after non-cardiac surgery, calculating sensitivity and specificity to a sum of combinations of indexes for each index set, and setting cutoff values for classification according to the sensitivity and specificity, and calculating a sum of indexes determined according to the index set preset for each variable, and classifying risk of acute kidney injury after non-cardiac surgery of the non-cardiac surgery patient on the basis of the cutoff values into four grades, and administering, based on the classified grade, an AKI preventive agent to the patient.