Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Abstract: An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Abstract: A method (of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium) includes: selecting first and second standard cells from a standard-cell-library; the first and second standard cells having corresponding first and second heights that are different from each other; stacking the first standard cell on the second standard cell to form a third cell; and including the third cell in a layout diagram. At least one aspect of the method is executed by a processor of a computer.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Abstract: A semiconductor device includes: fins configured to include: first active fins having a first conductivity type; and second active fins having a second conductivity type; and at least one gate structure formed over corresponding ones of the fins; and wherein the fins and the at least one gate structure are located in at least one cell region; and each cell region, relative to the second direction, including: a first active region which includes a sequence of three or more consecutive first active fins located in a central portion of the cell region; a second active region which includes one or more second active fins located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fins located between the first active region and a second edge of the cell region.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

Abstract: A circuit includes a level shifter circuit, an output circuit, and a first feedback circuit. The level shifter circuit is coupled to a first voltage supply, and configured to receive an enable signal, a first input signal or a second input signal, and to generate a first and second signal responsive to the enable signal or the first input signal. The output circuit coupled to the level shifter circuit and the first voltage supply, and configured to generate an output signal or a first feedback signal responsive to the first signal, and configured to latch a previous state of the output signal in response to the enable signal or an inverted enable signal. The first feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and configured to receive at least the enable signal, the inverted enable signal or the first feedback signal.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.

Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: An IC device includes first and second circuits adjacent each other and over a substrate. The first circuit includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second circuit includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second circuit or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connecting the first IO pattern and a second IO pattern of the second circuit. The second IO pattern is one of the plurality of conductive patterns of the second circuit and is along the first track.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: A device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. n intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line 48G. A second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.

Abstract: An IC structure includes first and second complementary field-effect transistors (CFETs) positioned in a semiconductor wafer, each of the first and second CFETs including a gate structure extending in a first direction, an n-type channel extending through the gate structure in a second direction perpendicular to the first direction, and a p-type channel extending through the gate structure in the second direction and aligned with the n-type channel in a third direction perpendicular to each of the first and second directions. A metal line extends in the first direction, is aligned with each of the first and second CFETs in the third direction, and is configured to distribute a power supply or reference voltage to each of the first and second CFETs. The metal line is a metal line closest to each of the first and second CFETs along the third direction and extending in the first direction.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.