Patents by Inventor Lee Chung Lu

Lee Chung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230275090
    Abstract: A semiconductor device includes a first cell in a first row, wherein the first row extends in a first direction, the first cell having a first cell height measured in a second direction perpendicular to the first direction. The semiconductor device further includes a second cell in the first row, wherein the second cell has a second cell height measured in the second direction, the second cell height is less than the first cell height. The second cell includes a first active region having a first width measured in the second direction, and a second active region having a second width measured in the second direction, wherein the second width is different from the first width.
    Type: Application
    Filed: June 10, 2022
    Publication date: August 31, 2023
    Inventors: Jiann-Tyng TZENG, Kam-Tou SIO, Shang-Wei FANG, Chun-Yen LIN, Sheng-Feng HUANG, Yi-Kan CHENG, Lee-Chung LU
  • Publication number: 20230275088
    Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Inventors: WEI-LING CHANG, LEE-CHUNG LU, XIANGDONG CHEN, KAM-TOU SIO, HSIANG-CHI HUANG
  • Publication number: 20230275081
    Abstract: A semiconductor device includes first and second cell rows, first to fourth fin shaped structures. The first cell row has a first row height. The second cell row is adjacent with the first cell row, and having a second row height. The first fin shaped structure extends across the first cell row. The second fin shaped structure extends across the first cell row, and separated from the first fin shaped structure. The third fin shaped structure extends across the second cell row. The fourth fin shaped structure extends across the second cell row, and separated from the third fin shaped structure. The first to fourth fin shaped structures are arranged in order along the first direction, each of the first, second and fourth fin shaped structure has a first conductive type, the third fin shaped structure has a second conductive type.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Zhong ZHUANG, Xiang-Dong CHEN, Lee-Chung LU, Tzu-Ying LIN, Yung-Chin HOU
  • Publication number: 20230253406
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Guo-Huei WU, Jerry Chang Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
  • Publication number: 20230253961
    Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master stage, and a slave stage including a first feedback inverter and a first transmission gate. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the first transmission gate includes first and second input terminals configured to receive the second and third clock signals.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Yung-Chen CHIEN, Xiangdong CHEN, Hui-Zhong ZHUANG, Tzu-Ying LIN, Jerry Chang Jui KAO, Lee-Chung LU
  • Publication number: 20230197723
    Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Inventors: Ali KESHAVARZI, Ta-Pen GUO, Shu-Hui SUNG, Hsiang-Jen TSENG, Shyue-Shyh LIN, Lee-Chung LU, Chung-Cheng WU, Li-Chun TIEN, Jung-Chan YANG, Ting Yu CHEN, Min CAO, Yung-Chin HOU
  • Publication number: 20230195991
    Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
    Type: Application
    Filed: February 7, 2023
    Publication date: June 22, 2023
    Inventors: Pin-Dai SUE, Po-Hsiang HUANG, Fong-Yuan CHANG, Chi-Yu LU, Sheng-Hsiung CHEN, Chin-Chou LIU, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Yi-Kan CHENG
  • Patent number: 11682671
    Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Ling Chang, Lee-Chung Lu, Xiangdong Chen, Kam-Tou Sio, Hsiang-Chi Huang
  • Patent number: 11682665
    Abstract: A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Zhong Zhuang, Xiang-Dong Chen, Lee-Chung Lu, Tzu-Ying Lin, Yung-Chin Hou
  • Patent number: 11677400
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lun Ou, Ji-Yung Lin, Yung-Chen Chien, Ruei-Wun Sun, Wei-Hsiang Ma, Jerry Chang Jui Kao, Shang-Chih Hsieh, Lee-Chung Lu
  • Patent number: 11664380
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei Wu, Jerry Chang Jui Kao, Chih-Liang Chen, Hui-Zhong Zhuang, Jung-Chan Yang, Lee-Chung Lu, Xiangdong Chen
  • Patent number: 11664383
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsueh-Chih Chou, Chia Hao Tu, Sang Hoo Dhong, Lee-Chung Lu, Li-Chun Tien, Ting-Wei Chiang, Hui-Zhong Zhuang
  • Patent number: 11637098
    Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Lee-Chung Lu, Po-Hsiang Huang, Chun-Chen Chen, Chung-Te Lin, Ting-Wei Chiang, Sheng-Hsiung Chen, Jung-Chan Yang
  • Publication number: 20230121153
    Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan CHANG, Kuo-Nan YANG, Chung-Hsing WANG, Lee-Chung LU, Sheng-Fong CHEN, Po-Hsiang HUANG, Hiranmay BISWAS, Sheng-Hsiung CHEN, Aftab Alam KHAN
  • Patent number: 11632102
    Abstract: A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Yung-Chen Chien, Xiangdong Chen, Hui-Zhong Zhuang, Tzu-Ying Lin, Jerry Chang Jui Kao, Lee-Chung Lu
  • Publication number: 20230109128
    Abstract: A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 6, 2023
    Inventors: Fong-Yuan Chang, Po-Hsiang Huang, Lee-Chung Lu, Jyh Chwen Frank Lee, Yii-Chian Lu, Yu-Hao Chen, Keh-Jeng Chang
  • Patent number: 11621703
    Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang-Jui Kao, Li-Chun Tien, Lee-Chung Lu
  • Publication number: 20230092284
    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 23, 2023
    Inventors: GREG GRUBER, CHI-LIN LIU, MING-CHANG KUO, LEE-CHUNG LU, SHANG-CHIH HSIEH
  • Publication number: 20230072698
    Abstract: A device includes a single standard cell. The single standard cell includes a first transistor region including a first extended active region extending between a first side cell boundary and a second side cell boundary opposite the first side cell boundary, and includes a plurality of source regions and one drain region. The single standard cell further includes a second transistor region including a second extended active region extending between the first side cell boundary and the second side cell boundary, and includes a source region and a single drain region.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Inventors: Lee-Chung LU, Li-Chun TIEN, Hui-Zhong ZHUANG, Chang-Yu WU
  • Publication number: 20230068280
    Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Cheng-Yu LIN, Jung-Chan YANG, Hui-Zhong ZHUANG, Sheng-Hsiung CHEN, Kuo-Nan YANG, Chih-Liang CHEN, Lee-Chung LU