Patents by Inventor Lee E. Cleveland

Lee E. Cleveland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11037624
    Abstract: Devices and methods for programming resistive change elements using an electrical stimulus are disclosed. According to some aspects of the present disclosure the devices and methods program at least one resistive change element within at least one resistive change element cell in a resistive change element array using an electrical stimulus having a voltage level greater than a steady state voltage level that can be supplied by a power supply.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 15, 2021
    Assignee: Nantero, Inc.
    Inventors: Jia Luo, Sheyang Ning, Lee E. Cleveland
  • Publication number: 20200388331
    Abstract: The present disclosure generally relates to combinations of resistive change elements and resistive change element arrays thereof. The present disclosure also generally relates to combinational resistive change elements and combinational resistive change element arrays thereof. The present disclosure additionally generally relates to devices and methods for programming and accessing combinations of resistive change elements. The present disclosure further generally relates to devices and methods for programming and accessing combinational resistive change elements.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Applicant: Nantero, Inc.
    Inventors: Jia Luo, Lee E. Cleveland, Ton Yan Tony Chan
  • Publication number: 20200098429
    Abstract: Devices and methods for programming resistive change elements using an electrical stimulus are disclosed. According to some aspects of the present disclosure the devices and methods program at least one resistive change element within at least one resistive change element cell in a resistive change element array using an electrical stimulus having a voltage level greater than a steady state voltage level that can be supplied by a power supply.
    Type: Application
    Filed: October 11, 2019
    Publication date: March 26, 2020
    Applicant: Nantero, Inc.
    Inventors: Jia Luo, Sheyang Ning, Lee E. Cleveland
  • Patent number: 10446228
    Abstract: Devices and methods for programming resistive change elements using an electrical stimulus are disclosed. According to some aspects of the present disclosure the devices and methods program at least one resistive change element within at least one resistive change element cell in a resistive change element array using an electrical stimulus having a voltage level greater than a steady state voltage level that can be supplied by a power supply.
    Type: Grant
    Filed: December 23, 2017
    Date of Patent: October 15, 2019
    Assignee: Nantero, Inc.
    Inventors: Jia Luo, Sheyang Ning, Lee E. Cleveland
  • Publication number: 20190198104
    Abstract: Devices and methods for programming resistive change elements using an electrical stimulus are disclosed. According to some aspects of the present disclosure the devices and methods program at least one resistive change element within at least one resistive change element cell in a resistive change element array using an electrical stimulus having a voltage level greater than a steady state voltage level that can be supplied by a power supply.
    Type: Application
    Filed: December 23, 2017
    Publication date: June 27, 2019
    Applicant: Nantero, Inc.
    Inventors: Jia Luo, Sheyang Ning, Lee E. Cleveland
  • Patent number: 6961267
    Abstract: Accurately programming a memory cell. A voltage is applied to a drain of the memory cell to program the cell. After applying the voltage, the cell is verified as to whether it is programmed to a desired level. The magnitude of the programming voltage is increased and applied to the drain, and the memory cell is re-verified for the desired level. This is repeated until the memory cell is programmed to the desired level. Additional memory cells are programmed in this fashion in order to program multiple memory cells in a narrow distribution around the desired level. The programming can be done one memory cell at a time or many cells can be programmed in parallel. Further a ramped programming voltage can applied to the gate of the memory cell(s), such that the ramped voltage to the gate and the ramped voltage to the drain both program the memory cell.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: November 1, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard M. Fastow, Lee E. Cleveland, Chi Chang
  • Patent number: 6957297
    Abstract: A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: October 18, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee E. Cleveland, Kendra Nguyen
  • Patent number: 6654848
    Abstract: A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: November 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee E. Cleveland, Kendra Nguyen
  • Patent number: 6400608
    Abstract: A technique is provided for reducing column leakage in a flash EEPROM device during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: June 4, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard Fastow, Sameer S. Haddad, Lee E. Cleveland
  • Patent number: 6292425
    Abstract: Power saving on the fly improves both the speed and power consumed in reading data from a core memory. Present data is selected from the core memory and clocked into the power saving arrangement. The present data is compared with previously selected data to determine whether the majority of data presently selected has changed from the previously selected data. In addition, the present selected data is also delayed and then subjected to a logical XOR function with the majority determination above. Finally, the data subjected to the logical XOR function and the majority determination are driven separately to external elements requesting the present data. Power is saved as the state of the majority of the data being driven from one data set to the next remains unchanged. Speed is increased as the data, once clocked into the arrangement, is driven in less than a clock pulse.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: September 18, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ali K. Al-Shamma, Lee E. Cleveland
  • Patent number: 6252803
    Abstract: A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: June 26, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard Fastow, Sameer S. Haddad, Lee E. Cleveland, Chi Chang
  • Patent number: 5973979
    Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: October 26, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chung K. Chang, Johnny C. Chen, Lee E. Cleveland
  • Patent number: 5852582
    Abstract: A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: December 22, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee E. Cleveland, Yuan Tang, Jonathan Su, Chi Chang, Chung K. Chang
  • Patent number: 5828601
    Abstract: A programmable reference used to identify a state of an array cell in a multi-density or low voltage supply flash EEPROM memory array. The programmable reference includes one or more reference cells, each reference cell having a floating gate which is programmed to control its threshold value. The array cells are read by applying an identical voltage to the gate of the array cell and the reference cell and comparing outputs to determine the array cell state. During read of an array cell, the programmable reference cell is biased the same as the array cell, so that the difference in threshold values between reference cells and array cells remain constant with a change in V.sub.CC. Circuitry is included for programming the reference cells utilizing a simple resistor ratio. Programming is performed at test time, preferably by the manufacturer, to assure V.sub.CC remains within strict tolerances.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: October 27, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shane C. Hollmer, Lee E. Cleveland
  • Patent number: 5793249
    Abstract: The system and method of enhancing the yield of flash memory circuit is disclosed. The method comprises performing a diagonal erase of a select group of memory cells on a wafer during sort. If the memory cells do not erase in a satisfactory manner, the control voltage applied to the memory cell is adjusted based on the memory cell's erase time. The circuitry for providing the adjustment voltage includes trimming circuitry for an incrementally increasing the applicable control of voltage.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: August 11, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jian Chen, Lee E. Cleveland
  • Patent number: 5708387
    Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: January 13, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee E. Cleveland, Johnny C. Chen
  • Patent number: 5650966
    Abstract: A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: July 22, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lee E. Cleveland, Johnny C. Chen
  • Patent number: 5612921
    Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: March 18, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chung K. Chang, Johnny C. Chen, Lee E. Cleveland
  • Patent number: 5579261
    Abstract: A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: November 26, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nader Radjy, Lee E. Cleveland, Jian Chen, Shane C. Hollmer
  • Patent number: 5576991
    Abstract: A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: November 19, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nader Radjy, Lee E. Cleveland, Jian Chen, Shane C. Hollmer