Abstract: A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.

Abstract: A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.

Abstract: A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.

Abstract: A gate power supply for supplying power to the gates of flash EEPROM memory cells in a multi-density or low voltage supply memory array to determine the states stored by the memory cells. The gate power supply includes a multi-phase voltage pump to increase voltage supplied to the gates of the memory cells above a system voltage supply, V.sub.CC to increase the working margin between memory cell states. The gate power supply further includes a low power supply standby pump to maintain the boosted voltage during an inactive mode. The wordline decoder for the memory is divided into sections with a large n-well parasitic capacitance of each decoder section acting as a reservoir to store the charge supplied by the low power standby pump. In an active mode, the parasitic capacitance in unselected decoder sections supplies power to the input of the selected diecoder section while the multi-phase pump is turning on.

Abstract: There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage V.sub.T distribution after erase is obtained without sacrificing any reduction in the erase speed.

Abstract: A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The distributed negative gate power supply includes a main charge pumping circuit (20a, 20b), a plurality of distribution sector pumping means (18a-18p). Each of the plurality of distribution sector pumping circuits is responsive to a half-sector select signal for selectively connecting the primary negative voltage to the wordlines of the selected half-sectors.

Abstract: A power-on reset circuit for generating and maintaining a reset signal in an active low state during power-up until a power supply voltage exceeds a predetermined level includes a resetting circuit (12a) and a control logic circuit (12b). The reset circuit is responsive to a monitoring signal, a start-up signal and a reference voltage for generating a reset signal which is initially in the active low state. The reset circuit includes a differential comparator (54) having a first input for receiving the start-up signal, a second input for receiving the reference voltage, and an output for generating the reset signal. The control logic circuit is responsive to the monitoring signal and the reset signal for generating a logic control signal which is initially in a high state. The differential comparator is responsive to the control signal and is activated only after the power supply voltage has exceeded a predetermined level so as to maintain initially the reset signal on its output in the low state.

Abstract: An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.

Abstract: An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto.

Abstract: An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors.

Abstract: A positive power supply for generating and supplying a regulated positive potential to control gates of selected memory cells via word lines in an array of flash EEPROM memory cells during programming includes a clock circuit (18b) for generating a pair of non-overlapping clock signals and charge pump means (18c) responsive to an external power supply potential (VCC) and to the non-overlapping clock signals for generating a high positive voltage. A regulator circuit (20) responsive to the high positive voltage and a reference voltage is provided for controlling the regulated positive potential so that it is independent of the external power supply potential (VCC).

Abstract: A negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pumping means (12) formed of a plurality of charge pump stages (401-404) for generating a high negative voltage, and cancellation means coupled to each stage of the charge pump means for effectively canceling out threshold voltage drops in the charge pump means. A regulator means (16) responsive to the high negative voltage and a reference potential is provided for generating the regulated negative potential so that it is independent of an external supply potential (VCC).

Abstract: A drain power supply for generating and supplying a regulated positive potential to drain regions of selected memory cells via bit lines in an array of flash EEPROM memory cells during programming includes charge pump means (20) formed of a plurality of charge pump sections (20a-20h) driven by one of a plurality of staggered clock signals for generating a moderately high level positive voltage. Cancellation means (26, 28) are coupled to each of the plurality of charge pump sections for effectively canceling out threshold voltage drops in the charge pump circuit. A regulator circuit (22) responsive to the regulated positive potential at an output node and a reference voltage is provided for generating a control voltage so as to control the high level positive voltage on the output node.