Patents by Inventor Lee Han Meng@Eugene Lee
Lee Han Meng@Eugene Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11791170Abstract: A method of making semiconductor packages includes providing a first lead frame having a first plurality of semiconductor dies arranged along a first longitudinal axis, each of the first plurality of semiconductor dies having a first number of metal contacts; providing a second lead frame having a second plurality of semiconductor dies arranged along a second longitudinal axis, each of the second plurality of semiconductor dies having a second number of metal contacts, the second number of metal contacts different than the first number of metal contacts; and covering the first plurality of semiconductor dies in a first mold using a common semiconductor die cavity; covering the second plurality of semiconductor dies in a second mold using the common semiconductor die cavity.Type: GrantFiled: April 22, 2021Date of Patent: October 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anis Fauzi Bin Abdul Aziz, Chong Han Lim, Lee Han Meng@Eugene Lee, Wei Fen Sueann Lim
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Patent number: 11742263Abstract: A leadframe for electronic systems comprising a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; and each link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.Type: GrantFiled: November 19, 2020Date of Patent: August 29, 2023Assignee: Texas Instruments IncorporatedInventors: Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 11626350Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.Type: GrantFiled: April 3, 2020Date of Patent: April 11, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chong Han Lim, Lee Han Meng@Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim, Siew Kee Lee
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Patent number: 11569152Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.Type: GrantFiled: January 23, 2019Date of Patent: January 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anis Fauzi Bin Abdul Aziz, Lee Han Meng@Eugene Lee, Wei Fen Sueann Lim, Siew Kee Lee
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Publication number: 20220223503Abstract: A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another.Type: ApplicationFiled: March 1, 2022Publication date: July 14, 2022Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi Bin Abdul Aziz, Sueann Wei Fen Lim, Jin Keong Lim
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Patent number: 11373940Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.Type: GrantFiled: September 22, 2020Date of Patent: June 28, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 11348806Abstract: A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.Type: GrantFiled: December 23, 2014Date of Patent: May 31, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Shu Hui Ooi, Anis Fauzi Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 11264310Abstract: A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another.Type: GrantFiled: June 4, 2020Date of Patent: March 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng Eugene Lee, Anis Fauzi Bin Abdul Aziz, Sueann Wei Fen Lim, Jin Keong Lim
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Publication number: 20210384110Abstract: A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Inventors: Lee Han Meng Eugene Lee, Anis Fauzi Bin Abdul Aziz, Sueann Wei Fen Lim, Jin Keong Lim
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Publication number: 20210242038Abstract: In accordance with at least one example of the disclosure, a system comprises a semiconductor package, comprising a first side surface having a first set of metal contacts extending therefrom; a second side surface having a second set of metal contacts extending therefrom; a top surface; a bottom surface; and an end surface meeting at least one of the first side surface, the second side surface, the top surface, and the bottom surface at a non-rounded edge.Type: ApplicationFiled: April 22, 2021Publication date: August 5, 2021Inventors: Anis Fauzi BIN ABDUL AZIZ, Chong Han LIM, Lee Han Meng@Eugene LEE, Wei Fen Sueann LIM
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Patent number: 11056462Abstract: A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.Type: GrantFiled: July 10, 2017Date of Patent: July 6, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng @ Eugene Lee, Wei Fen Sueann Lim, Anis Fauzi Bin Abdul Aziz
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Publication number: 20210202356Abstract: A method includes forming a leadframe assembly to have a pair of opposing sides, and having semiconductor die receiving portions extending between the opposing sides. The method also includes placing semiconductor dies on the leadframe assembly in the die receiving portions. Each die has a row of leads on each of two opposing sides of the die and a longitudinal axis parallel to the rows of leads. The longitudinal axis of each die is orthogonal to the opposing sides of the leadframe assembly. The method further includes applying mold compound to the semiconductor dies. The method includes punching through the leadframe assembly between the opposing sides using a first tool having a first tool longitudinal axis parallel to longitudinal axes of the dies.Type: ApplicationFiled: April 3, 2020Publication date: July 1, 2021Inventors: Chong Han LIM, Lee Han Meng@Eugene LEE, Anis Fauzi BIN ABDUL AZIZ, Wei Fen, Sueann LIM, Siew Kee LEE
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Publication number: 20210074613Abstract: A leadframe for electronic systems comprising a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; and each link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.Type: ApplicationFiled: November 19, 2020Publication date: March 11, 2021Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen, Sueann Lim
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Publication number: 20210043466Abstract: In accordance with at least one example of the disclosure, a system comprises a semiconductor package, comprising a first side surface having a first set of metal contacts extending therefrom; a second side surface having a second set of metal contacts extending therefrom; a top surface; a bottom surface; and an end surface meeting at least one of the first side surface, the second side surface, the top surface, and the bottom surface at a non-rounded edge.Type: ApplicationFiled: August 6, 2019Publication date: February 11, 2021Inventors: Anis Fauzi BIN ABDUL AZIZ, Chong Han LIM, Lee Han Meng@Eugene LEE, Wei Fen Sueann LIM
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Publication number: 20210005540Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 10879154Abstract: A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second sub-leadframe connected by tiebars (111, 121) to a frame (130); and each link having a neck (151) suitable for bending the link, the necks arrayed in a line (170) operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.Type: GrantFiled: October 6, 2016Date of Patent: December 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Anis Fauzi Bin Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 10804114Abstract: A method for forming a multilevel leadframe for an integrated circuit is provided. A conductive sheet is etched from one side to form a thinner region within a frame region for leads lines and bond pads. The conductive sheet is etched to form a plurality of bond pads in a first level of the thinner region arranged in at least a first row and a second row. Each bond pad has a pad width and is separated from an adjacent bond pad by a bond pad clearance distance. The conductive sheet is etched from an opposite side to form a plurality of lead lines in a second level of the thinner region having a line width and is separated from an adjacent lead line by at least a lead line clearance distance. Each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the second level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.Type: GrantFiled: April 26, 2016Date of Patent: October 13, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, You Chye How
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Patent number: 10784190Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.Type: GrantFiled: August 18, 2017Date of Patent: September 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Wei Fen Sueann Lim
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Publication number: 20200235042Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Applicant: Texas Instruments IncorporatedInventors: Anis Fauzi Bin Abdul Aziz, Lee Han Meng@Eugene Lee, Wei Fen Sueann Lim, Siew Kee Lee
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Patent number: 10720406Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.Type: GrantFiled: November 19, 2019Date of Patent: July 21, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Khoo Yien Sien