Abstract: An exemplary active matrix organic light emitting diode (OLED) display includes a data line, a current sensing line, a power line and a plurality of pixels all electrically coupled to the data line, the current sensing line and the power line. During a data current is writing to a selected one of the pixels, the selected pixel draws a current from the current sensing line, and the data line supplies a particular data voltage to the selected pixel according to the drawn current from the current sensing line until the drawn current matched with the data current; the other non-selected pixels draw currents from the power line for light-emission. Moreover, a pixel circuit and a data current writing method adapted for the above-mentioned active matrix OLED display also are provided.

Abstract: A pixel structure is disposed in a display region which includes a light-emitting region and a non-light-emitting region. The pixel structure has a first active device, a second active device, a light emitting device and an auxiliary electrode layer. The first active device is electrically connected with a scan line and a data line. The second active device is electrically connected with the first active device and a power line. The light emitting device is disposed in the light-emitting region and includes a first electrode layer electrically connected with the second active device, a light emitting layer disposed on the first electrode layer and a second electrode layer disposed on the light emitting layer. The auxiliary electrode layer is electrically connected with the power line.

Abstract: An electroluminescence device includes a substrate, a pixel array, lead line sets, driving devices and at least one power transmission pattern. The substrate has a display region and a peripheral circuit region. The pixel array is disposed in the display region and includes pixel structures. Each pixel structure has at least one active element and a light emitting element. The lead line sets are disposed in the peripheral circuit region and electrically connected to the pixel array, and each lead line set has multiple lead lines. Each driving device is electrically connected to one lead line set. The power transmission pattern is disposed in the peripheral circuit region and between adjacent lead line sets. One end of the power transmission pattern is electrically connected to the light emitting element and another end of the power transmission pattern is electrically connected to one corresponding driving device.

Abstract: A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end.

Abstract: A display panel has a plurality of OLED pixels arranged in rows and columns. The pixel driving circuit has two or more current paths through a plurality of switching elements for providing the necessary current to the OLEDs in a pixel. The control end of each switching element is connected to the control end of the other switching elements, but each switching element has a separate power source which can be separately adjustable. In some embodiments, in a pixel or sub-pixel, one switching element is located at one end and one switching element is located at the other end of a pixel length, and each pixel is adjacent to a first power source line and a second power source line along the pixel length for separately providing the electrical power to two switching elements.

Abstract: A gate driver on array of a display includes a substrate having a peripheral region, and a gate driver on array structure formed in the peripheral region. The gate driver on array structure includes a pull-down transistor, and the pull-down transistor has a gate electrode, an insulating layer, a semiconductor island, a source electrode, and a drain electrode. The semiconductor island extends out of both edges of the gate electrode, and extends out of an edge of the source electrode and an edge of the drain electrode.

Abstract: A gate driver-on-array structure for using in a display panel including first conductive patterns, semiconductor patterns, second conductive patterns, third conductive patterns, first electrode line, and first connectors is provided. The first conductive patterns, the second conductive patterns, the semiconductor patterns and the third conductive patterns together form a plurality of thin film transistors. The first electrode line is located at a side of the first conductive patterns and spaced from the first conductive patterns by a first distance. The first connectors are connected to the corresponding first conductive patterns and the first electrode line.

Abstract: A shift register of an LCD device operates based on two clock signals and maintains the gate voltage of an output transistor switch using two pull-down transistor switches. The gate voltages of the pull-down transistor switches are switched periodically between the high and low level of the clock signals. During the output period, the transistor switches have negative gate-source voltages so as to reduce leakage.

Abstract: A gate driver includes several first and second circuit units outputting first and second driving signals to odd and even gate lines, respectively, and each of the first circuit units or the second circuit units includes a signal output unit for outputting the driving signal and a shift register unit for outputting a start signal to a next circuit unit. A driving method is also disclosed.

Abstract: A shift register capable of turning on a feedback register includes a signal generating circuit for generating an output signal at an output end of the shift register according to a first clock signal while the signal generating circuit is being turned on, a driving circuit, electrically coupled to the signal generating circuit, for generating a driving signal to control the signal generating circuit according to an input signal received by an input end of the shift register, a feedback circuit, electrically coupled to a next stage shift register, for transmitting a control signal while the feedback circuit is being turned on by the next stage shift register, and a control switch, electrically coupled to the signal generating circuit and the feedback circuit, for turning off the signal generating circuit while the control switch is being turned on by the control signal transmitted from the feedback circuit.

Abstract: A shift register for use in an LCD is disclosed. The shift register provides better gate driving signals with the lower coupling effect. The shift register includes two switches. The control node of the first switch is electrically coupled to the control node of the second switch. One end of the first switch receives a clock signal, and the other end of the first switch is electrically coupled to one end of the second switch. The other end of the second switch outputs a gate driving signal. Both of the two switches are controlled by a control signal.

Abstract: An active device array substrate including a substrate, scan lines, data lines, pixels, a bus line and voltage pull-down circuits is provided. The pixels disposed on intersections of the scan lines and the data lines are arranged in array on the substrate and are electrically connected to the scan lines and the data lines. Each of the voltage pull-down circuits including a transistor and an electrostatic discharge protection device is electrically connected between the scan line and the bus line correspondingly. Each transistor includes a source, a drain, and a gate electrically connected to a next scan line. Each gate is electrically connected to the scan line, the source, the drain and the bus line correspondingly through the electrostatic discharge protection device. The electrostatic discharge protection of the active device array substrate is enhanced effectively by the electrostatic discharge protection device.

Abstract: A shift register includes a signal generating circuit for generating an output signal at an output end of the shift register according to a first clock signal while the signal generating circuit is turned on; a driving circuit, electrically coupled to the signal generating circuit, for generating a driving signal to control the signal generating circuit according to an input signal received from an input end of the shift register; a feedback circuit, electrically coupled to a next stage shift register, for transmitting a control signal while the feedback circuit is turned on by the next stage shift register; and a control switch, electrically coupled to the signal generating circuit and the feedback circuit, for turning off the signal generating circuit while the control switch is turned on by the control signal from the feedback circuit.

Abstract: In a display device and a repairing method therefor, the display device includes a gate line and two gate-on-array circuits arranged at two sides thereof. Each of the gate-on-array circuits includes a stage coupled to the gate line. Each the stage includes a transistor and a repair circuit. The first source/drain electrode of the transistor is coupled to the gate line, and the second source/drain electrode of the transistor is coupled to receive a clock pulse signal. The repair circuit includes a first terminal coupled to the gate electrode of the transistor, a second terminal coupled to a predetermined potential, and at least one control terminal adapted to receive at least one repair signal to pull the potential on the gate electrode of the transistor to the predetermined potential. The transistor maintains at off-state when the at least one repair signal is supplied to the repair circuit.

Abstract: A gate driver-on-array structure integrated in a display panel includes a bar-like conductive layer, a semiconductor layer, first conductive patterns, second conductive patterns, a first electrode line and a second electrode line. The bar-like conductive layer has a plurality of regions. The semiconductor layer is disposed within the regions of the bar-like conductive layer. The first conductive patterns and the second conductive patterns are disposed on the semiconductor layer and located within the regions. The bar-like conductive layer is located between the first electrode line and the second electrode line. The first electrode line and the second electrode line are respectively spaced from the bar-like conductive layer by a first distance and a second distance. The GOA structure has first connectors connected to the corresponding first conductive patterns and the first electrode line, and second connectors connected to the second conductive patterns and the second electrode line.

Abstract: An active device array substrate is provided. The active device array substrate includes a plurality of pixel units. Each of the pixel units includes a first active device, a first scan line, a second active device, a second scan line, a data line, a common line, and a pixel electrode. The first scan line is electrically connected to a first gate of the first active device. The second scan line is electrically connected to a second gate of the second active device. The data line is electrically connected to a first source of the first active device. The common line is electrically connected to a second source of the second active device. The pixel electrode is electrically connected to a first drain of the first active device and a second drain of the second active device.

Abstract: A gate driving circuit having a low leakage current control mechanism is disclosed for providing a plurality of gate signals forwarded to a plurality of gate lines respectively. The gate driving circuit includes a plurality of shift registers. Each shift register includes a driving unit, an energy store unit, a buffer unit, a voltage regulation unit, and a control unit. The driving unit generates a gate signal based on a driving control voltage and a first clock. The buffer unit functions to receive a start pulse signal. The energy store unit provides the driving control voltage through performing a charging process based on the start pulse signal. The control unit generates a control signal based on the first clock and a second clock having a phase opposite to the first clock. The voltage regulation unit regulates the driving control voltage based on the control signal.

Abstract: A gate driver-on-array structure for using in a display panel including first conductive patterns, semiconductor patterns, second conductive patterns, third conductive patterns, first electrode line, and first connectors is provided. The first conductive patterns, the second conductive patterns, the semiconductor patterns and the third conductive patterns together form a plurality of thin film transistors. The first electrode line is located at a side of the first conductive patterns and spaced from the first conductive patterns by a first distance. The first connectors are connected to the corresponding first conductive patterns and the first electrode line.

Abstract: An apparatus, a shifter register unit, a liquid crystal display device and a method for eliminating afterimage are provided herein, which merely utilize a high voltage source delay discharging phenomenon oriented from a powered-off power device to lead any two of a plurality of existing signal sources employed by the shift register unit to reach a high level used for controlling of charge and discharge of a discharge switching unit corresponding to a pixel unit. Therefore, a power-off afterimage problem could be improved and a signal reset function for power-on also can be achieved.

Abstract: A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end.