Abstract: A voltage pull-down circuit electrically connected between two scan lines and a bus line includes a transistor and an electrostatic discharge protection device. Each transistor comprises a source, a drain, and a gate electrically connected to one of the scan lines. Each gate is connected to another scan line, the source, and the drain through the electrostatic discharge protection device.

Abstract: A pixel driving method applied to a flat panel display is provided. In a first time period, an Nth scan line provides a first scan voltage to a pixel row to conduct the corresponding thin film transistors (TFT). Also, an N+1th scan line provides a second scan voltage through the conducted TFTs to the corresponding first switches to conduct the first switches, and then a number of first data voltages of the corresponding data lines are outputted to the corresponding first pixel electrodes. The absolute value of the difference between the first scan voltage and the second scan voltage is not smaller than a threshold voltage of each TFTs.

Abstract: An active device array substrate is provided. The active device array substrate includes a plurality of pixel units. Each of the pixel units includes a first active device, a first scan line, a second active device, a second scan line, a data line, a common line, and a pixel electrode. The first scan line is electrically connected to a first gate of the first active device. The second scan line is electrically connected to a second gate of the second active device. The data line is electrically connected to a first source of the first active device. The common line is electrically connected to a second source of the second active device. The pixel electrode is electrically connected to a first drain of the first active device and a second drain of the second active device.

Abstract: In a method of making device of a display, an insulating layer, a semiconductor layer, an ohmic contact layer, a second conductive layer, and a photoresist pattern are consecutively formed on a first conductive structure. The photoresist pattern includes a first thickness region, and a second thickness region outside the first thickness region. The thickness of the second thickness region is smaller than that of the first thickness region. In addition, in a gate driver on array (GOA) of a display, it includes a gate driver on array structure with a pull-down transistor. The pull-down transistor has a gate electrode, a semiconductor island, a source electrode and a drain electrode. The semiconductor island extends out of the edges of the gate electrode, the source electrode, and the drain electrode.

Abstract: A display apparatus and a circuit reparation method thereof are provided. The display apparatus comprises a control module, a first gate on array (GOA) circuit, a second GOA circuit, and a variable voltage source. The control module generates at least one control signal. The first GOA circuit is electrically connected to the control module according to a first leading wire in advance. The second GOA circuit is electrically connected to the control module according to a second leading wire in advance. The variable voltage source provides a predetermined voltage level. When the first GOA circuit is disabled, the first GOA circuit and the control module are adjusted to be electrically disconnected, and the first leading wire is electrically connected to the variable voltage source. The display apparatus is operated in response to the control signal and the predetermined voltage level.

Abstract: A shift register includes a plurality of register stages. Each register stage includes an output circuit, a first switching circuit and a second switching circuit. The output circuit is capable of outputting a first driving signal. The first switching circuit is used to pull down the output circuit into a low voltage level when the output circuit is not outputting the first driving signal. The second switching circuit is capable of receiving an input signal. The first switching circuit holds electric charges by the parasitical capacitor resident in the transistor in order to keep the first switching circuit in a turn-on state when the output circuit is not outputting the first driving signal.

Abstract: A gate driver-on-array structure integrated in a display panel includes a bar-like conductive layer, a semiconductor layer, first conductive patterns, second conductive patterns, a first electrode line and a second electrode line. The bar-like conductive layer has a plurality of regions. The semiconductor layer is disposed within the regions of the bar-like conductive layer. The first conductive patterns and the second conductive patterns are disposed on the semiconductor layer and located within the regions. The bar-like conductive layer is located between the first electrode line and the second electrode line. The first electrode line and the second electrode line are respectively spaced from the bar-like conductive layer by a first distance and a second distance. The GOA structure has first connectors connected to the corresponding first conductive patterns and the first electrode line, and second connectors connected to the second conductive patterns and the second electrode line.

Abstract: An active device array substrate including a substrate, scan lines, data lines, pixels, a bus line and voltage pull-down circuits is provided. The pixels disposed on intersections of the scan lines and the data lines are arranged in array on the substrate and are electrically connected to the scan lines and the data lines. Each of the voltage pull-down circuits including a transistor and an electrostatic discharge protection device is electrically connected between the scan line and the bus line correspondingly. Each transistor includes a source, a drain, and a gate electrically connected to a next scan line. Each gate is electrically connected to the scan line, the source, the drain and the bus line correspondingly through the electrostatic discharge protection device. The electrostatic discharge protection of the active device array substrate is enhanced effectively by the electrostatic discharge protection device.

Abstract: A gate driver includes several first and second circuit units outputting first and second driving signals to odd and even gate lines, respectively, and each of the first circuit units or the second circuit units includes a signal output unit for outputting the driving signal and a shift register unit for outputting a start signal to a next circuit unit. A driving method is also disclosed.

Abstract: A shift register circuit including a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit connected in serial. The second shift register unit includes an output terminal, and a pull down system pulling the voltage of the output terminal of the second shift register unit according to a pull down signal. The fourth shift register unit includes a third switch and a fourth switch. The fourth switch has a control terminal electrically coupled to the second terminal of the third switch and the pull down unit. The fourth shift register unit generates the pull down signal according to the voltage level of the connecting point between the third switch and the fourth switch.

Abstract: A protection circuit of an LCD panel. The LCD panel includes a display cell coupled between a data electrode, a gate electrode and a common electrode. A switch includes a first terminal and a second terminal. The first terminal is coupled to the data electrode, the gate electrode or both. The switch is turned on when a voltage level of the first terminal or the second terminal exceeds a threshold voltage. An ESD protection circuit includes a capacitive load and a resistive load, coupled between the second terminal and the common electrode.

Abstract: A driving circuit includes a plurality of connected driving circuit units, and each of the driving circuit units includes an input unit, an output unit, a first control unit, a second control unit, and a pull-down circuit. Each of the driving circuit units receives a start signal and a clock signal to output an output signal to a next driving circuit unit. The first control unit, the second control unit, and the pull-down circuit are used to release the accumulative charges of the circuit and stabilize the output signal.

Abstract: A driving circuit controlled with a clock signal to drive scan lines of a liquid crystal display includes cascade-connected driving circuit units, and each of the driving circuit units includes an input unit, an output unit, a pull-down circuit, and a control unit. The input unit receives a start signal, and the output unit outputs a driving signal and a carry signal, and the pull-down circuit and the control unit stabilizes the driving signal and the carry signal to prevent the circuit errors.

Abstract: A control circuit includes a plurality of shift register stages. Each shift register stage is capable of outputting an individual output signal. The output signal is utilized to be a driving signal of next shift register stages. Each shift register stage comprises a transistor for receiving a clear signal CLR. The residual charges of the shift register stage can be released when the clear signal CLR is in a high voltage level. The clear signal CLR is enabled during a non-blanking time of a liquid crystal display (LCD). Each current register stage can use an output signal of another shift register stage which is apart from the current shift register stage by a predetermined interval as the clear signal CLR. The clear signal CLR is used to release the residual charges of the shift register stage before the shift register stage outputs its own output signal.

Abstract: A flat display apparatus comprising a shift register array is provided. The shift register array comprises a plurality of shift registers. At least one of these shift registers comprises a shift register unit, a first TFT, and a second TFT. The shift register unit is configured to receive an activation signal and comprises a first output terminal and a second output terminal. The gate of the first TFT is coupled to the first output terminal. The second electrode of the first TFT receives a clock signal. The gate of the second TFT is coupled to the first electrode of the first TFT. The second electrode of the second TFT is coupled to the second electrode of the first TFT. The first electrode of the second TFT is coupled to the second output terminal.

Abstract: A shift register includes a plurality of register stages. Each register stage includes an output circuit, a first switching circuit and a second switching circuit. The output circuit is capable of outputting a first driving signal. The first switching circuit is used to pull down the output circuit into a low voltage level when the output circuit is not outputting the first driving signal. The second switching circuit is capable of receiving an input signal. The first switching circuit holds electric charges by the parasitical capacitor resident in the transistor in order to keep the first switching circuit in a turn-on state when the output circuit is not outputting the first driving signal.

Abstract: A shift register for use in an LCD is disclosed. The shift register provides better gate driving signals with the lower coupling effect. The shift register includes two switches. The control node of the first switch is electrically coupled to the control node of the second switch. One end of the first switch receives a clock signal, and the other end of the first switch is electrically coupled to one end of the second switch. The other end of the second switch outputs a gate driving signal. Both of the two switches are controlled by a control signal.

Abstract: A pixel driving method applied to a flat panel display is provided. In a first time period, an Nth scan line provides a first scan voltage to a pixel row to conduct the corresponding thin film transistors (TFT). Also, an N+1th scan line provides a second scan voltage through the conducted TFTs to the corresponding first switches to conduct the first switches, and then a number of first data voltages of the corresponding data lines are outputted to the corresponding first pixel electrodes. The absolute value of the difference between the first scan voltage and the second scan voltage is not smaller than a threshold voltage of each TFTs.

Abstract: A shift register circuit including a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit connected in serial. The second shift register unit includes an output terminal, and a pull down system pulling the voltage of the output terminal of the second shift register unit according to a pull down signal. The fourth shift register unit includes a third switch and a fourth switch. The fourth switch has a control terminal electrically coupled to the second terminal of the third switch and the pull down unit. The fourth shift register unit generates the pull down signal according to the voltage level of the connecting point between the third switch and the fourth switch.

Abstract: A flat display structure including a substrate, a pixel matrix, a driving circuit and several voltage adapting devices and driving method thereof are provided. Each of voltage adapting devices includes an input terminal, a first control terminal and an output terminal. The input terminal is electrically connected to the i-th gate line Gi corresponding to the i-th pixel row Ri. The first control terminal is adapted to receive a first control signal. The output terminal is adapted to receive a working voltage.