Abstract: A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

Abstract: Described is an apparatus which comprises: a power supply node; a plurality of inductors inductively coupled with one another, wherein at least one inductor of the plurality is electrically coupled to the power supply node; a plurality of loads; and a plurality of capacitors coupled to the plurality of inductors, respectively, and also coupled to the plurality of loads, respectively.

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

Abstract: A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.

Abstract: A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

Abstract: Methods and apparatus relating to a compact partitioned capacitor design for multiple voltage and/or load domains (e.g., with improved decoupling) are described. In an embodiment, a capacitor provides substrate decoupling for a plurality of loads. Moreover, the capacitor is capable of decoupling two or more voltage domains. Furthermore, in some embodiments the capacitor is capable of decoupling two or more voltage domains and mitigating self-noise and/or cross-noise between them. Other embodiments are also disclosed and claimed.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: Semiconductor device assemblies include at least first and second semiconductor dice disposed in a face-to-face configuration. At least some of a plurality of conductive structures are electrically and structurally coupled to a bond pad of the first semiconductor die and a bond pad of the second semiconductor die. A first end of each of a plurality of laterally extending conductive elements may be structurally and electrically coupled to a conductive terminal of a substrate, and a second end of each laterally extending conductive element is structurally and electrically coupled to at least one of a bond pad of the first semiconductor die, a bond pad of the second semiconductor die, and a conductive structure. Methods include the fabrication of such assemblies. Electronic systems include at least one electronic signal processing device, at least one input or output device, and at least one memory device including such a semiconductor device assembly.

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

Abstract: Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side, a first terminal at the active side, and integrated circuitry electrically coupled to the first terminal. The first die also includes a first redistribution structure at the active side of the first die. The microelectronic device can also include a second known good microelectronic die attached to the first die in a stacked configuration such that a back side of the second die is facing the support member and an active side of the second die faces away from the support member. The second die includes a second redistribution structure at the active side of the second die.

Abstract: A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer.

Abstract: A lead frame-based semiconductor device package including at least one land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. The terminal pads of the interposer substrate may be electrically connected to both a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. The assembly is overmolded with an encapsulant, leaving the opposing side of the interposer substrate free of encapsulant. Lead fingers of a lead frame superimposed on the opposing side of the interposer substrate are bonded directly to the land grid array lands.