Abstract: The systems and methods disclosed herein, in one aspect thereof, can encrypt and decrypt messages using a multivariate extended Clipped Hopfield neural network that uses a Diffie-Hellman like key exchange algorithm. The proposed cryptosystem comprises three stages that are involved in the communication. A first stage, where parameters are initialized and private keys are generated, a second stage where various base matrix pairs and threshold vectors are synchronized between the sender and the recipient, and a third stage, where encryption/decryption is performed.

Abstract: The systems and methods disclosed herein, in one aspect thereof, can encrypt and decrypt messages using a multivariate extended Clipped Hopfield neural network that uses a Diffie-Hellman like key exchange algorithm. The proposed cryptosystem comprises three stages that are involved in the communication. A first stage, where parameters are initialized and private keys are generated, a second stage where various base matrix pairs and threshold vectors are synchronized between the sender and the recipient, and a third stage, where encryption/decryption is performed.

Abstract: A digital chip system, digital chip, methods for embedding data and methods for extracting data are provided. In some embodiments, a digital chip includes: a watermark encoder digital chip configured to receive one or more watermark bits and generate a stego-video; and a watermark decoder digital chip configured to receive the stego-video and extract the one or more watermark bits from the stego-video. In some embodiments, the digital chip also includes: a video decoder controller digital chip configured to receive raw video data, wherein the raw video data is received from a video decoder; a configuration controller digital chip configured to configure the video decoder; a memory management unit digital chip configured to store at least one of the raw video frame, the raw video data or the stego-video; and an Ethernet controller unit digital chip configured to store or access the raw video or stego-video.

Abstract: A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller.

Abstract: A digital chip system, digital chip, methods for embedding data and methods for extracting data are provided. In some embodiments, a digital chip includes: a watermark encoder digital chip configured to receive one or more watermark bits and generate a stego-video; and a watermark decoder digital chip configured to receive the stego-video and extract the one or more watermark bits from the stego-video. In some embodiments, the digital chip also includes: a video decoder controller digital chip configured to receive raw video data, wherein the raw video data is received from a video decoder; a configuration controller digital chip configured to configure the video decoder; a memory management unit digital chip configured to store at least one of the raw video frame, the raw video data or the stego-video; and an Ethernet controller unit digital chip configured to store or access the raw video or stego-video.

Abstract: A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller.

Abstract: A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller.

Abstract: A pad-free radio-frequency mouse includes an ergonomic design such that the mouse is contoured to a user's hand, a Radio-Frequency mouse transmitter, and a USB Radio-Frequency receiver. With the usual mouse pad removed, the cursor on a monitor can be subtly maneuvered by moving one's thumb or fingers over an optical sensor in the mouse. Practically all functions found in existing mice and new functions can be implemented via five or more buttons provided adjacent the optical sensor.

Abstract: A Wiegand Converter for generating a bi-directional data includes a Terminal Data Separator, a Switch Controller, a Bi-directional Switch to control the Input or Output Wiegand Data send through a Bi-directional Wiegand Data Line. The Received Data sent to Converter and Transmitted Data received From Converter are in recognized computer form such as ASCII. The unsecured Wiegand protocols can then be manipulated by a terminal or transmitted it via a secured form or different data communication protocols and reversed it back to an acceptable Wiegand form for controlling the devices to be located at remote sites or in separate compartments.

Abstract: A sequence generator for generating a pseudo random sequence for random number generation or a stream cipher engine includes a plurality of linear feedback shift registers operable to generate a plurality of binary sequences. A plurality of nonlinear functions having the binary sequences as their input and operable to generate a second plurality of binary sequences. There are at least two switches and a controller including a shift register operable to control said first and second switches. The first switch is operative to select one of the second plurality of binary sequences to the first bit of the shift register, and the second switch is operative to select one of said second plurality of binary sequences to the output of the sequence generator.

Abstract: A compact dual function Random Number Generator and Stream Cipher Generator includes a Crypto-engine has a controller for controlling the engine to operate in one or other of its functions. The Crypto-engine incorporates a plurality of clipped Hopfield Neural Network pairs.

Abstract: A compact dual function Random Number Generator and Stream Cipher Generator includes a Crypto-engine has a controller for controlling the engine to operate in one or other of its functions. The Crypto-engine incorporates a plurality of clipped Hopfield Neural Network pairs.

Abstract: A sequence generator for generating a pseudo random sequence for random number generation or a stream cipher engine includes a plurality of linear feedback shift registers operable to generate a plurality of binary sequences. A plurality of nonlinear functions having the binary sequences as their input and operable to generate a second plurality of binary sequences. There are at least two switches and a controller including a shift register operable to control said first and second switches. The first switch is operative to select one of the second plurality of binary sequences to the first bit of the shift register, and the second switch is operative to select one of said second plurality of binary sequences to the output of the sequence generator.

Abstract: An extender (10) comprises a first, male section (12) and a second, female section (14) adapted to be back-to-back assembled. A pair of latches devices (39, 52) are provided on both opposite ends of the male section (12) and female section (14) for fastening the male section (12) and the female section (14) together. A plurality of first passageways (32) are formed in the male section (12) and a corresponding number of second passageways (58) are formed in the female section (14) wherein each of the first passageways (32) cooperates with the aligned corresponding second passageway (58) to form a contact receiving passage for receiving a corresponding contact (80) therein. A pair of grounding tangs (70) are disposed at two opposite ends of the extender (10) wherein each grounding tang (70) comprises an outward facing first portion (72) positioned in the male section (12), and an inward facing second portion (74) positioned in the female section (14).

Abstract: A card edge socket connector (1) includes an insulative elongated housing (10) having a plurality of contact slots (14) side by side vertically extending therethrough. A plurality of contacts (90) are received within the corresponding contact slots (14), respectively. A central board slot (12) extends in the housing (10) in the lengthwise direction for reception of the bottom edge portion of daughter board (100) inserted therein whereby the contacts (90) are electrically engaged with the traces on the bottom edge portion of the daughter board (100). An ejector (50) is pivotally positioned in a cavity (30) at one end of the housing (10) and a pair of separate latches (70) are positioned adjacent such ejector (50) but segregative and spaced therefrom by substantially a portion of the insulative housing (10) for latchably sandwiching and engaging within a retaining (92) hole of the daughter board (100) when the daughter board (100) is received in the board slot (12) in the connector housing (10).

Abstract: An electrical connector (10) includes an insulative housing (12) with a plurality of contacts. Adjacent either end of the housing (12) a boardlock (20) and a post (40) are arranged to be aligned with each other in a front-to-end direction. The boardlock (20) generally includes a first vertical section (22) for engagement with the corresponding grounding tang of a complementary connector, and a second vertical section (24) with the downward extending retention legs (25) for extending through a first corresponding hole (102) in the PC board (100), and an upward guiding tab (26). The post (40) includes a horizontal section (42) for retaining the post (40) within the housing (12), and a vertical lug section (46) for extending through a second corresponding hole (104) in the PC board (100).

Abstract: A connector (10) includes a housing (12) defining a plurality of passageways (16) for receiving a corresponding number of contacts therein. The housing (12) further includes three projection bars (20) extending rearward from a rear surface (18) of the housing (12) for protectively accommodating the corresponding plural contact tails therebetween. A mounting device (22) includes a pair of individual mounting ears (24, 24') which are relatively closely side by side positioned within two juxtaposed slots (38, 38') of the housing (12) wherein each mounting ear (24, 24') has a retention section (28, 28') interferentially embedded within a retention slit (44, 44') for fastening the mounting ear (24, 24') to the housing (12), and an L-shaped mounting section (32, 32') closely beside one side surface (36, 36') of the bar (20).

Abstract: An IDC type terminator (10) includes a housing (12) having a plurality of passageways (18) extending therethrough in the vertical direction. A plurality of contacts (20) are respectively received within the corresponding passageways (18). The upper and lower portions of the contacts (20) respectively and oppositely extending out of the housing (12) wherein the upper portions engage the PC board (15) which vertically stands on the housing (12), and the lower portions engage the corresponding flat cable (34) which is sandwiched between a bottom cover (16) and the housing (12). Opposite to the bottom cover (16), a top cover (14) is attached to the housing (12) for shielding the PC board (15) therein. A pair of cavities (22) are positioned on two opposite ends of the housing (12) so that the latches (58, 64) of the top cover (12) and of the bottom cover (14) may commonly but oppositely side by side occupy the corresponding cavity (22).

Abstract: An interconnection system includes a hard disc drive (24) having a standard header connector (101, 30) that can be electrically connected to one type of computer housing connector (102) by use of a flat cable (104) or, alternatively, can be attached to an adapter (26) to enable the hard disc drive to be slidably inserted into a cavity (14) of a more advanced type of computer to be electrically connected to another type of computer housing connector (16), i.e., a card edge connector. The adapter (26) includes a housing (52) defining a number of passageways (58) receiving a receiving portion of a number of contacts (60) which are connected with contacts of the header connector (30) in which a portion of the housing (52) is exposed to an exterior with regard to the header connector, and a blade (54) receiving a tail portion (68) of the contacts (60) for connection with contacts of the connector (16).

Abstract: A shorting block (10) includes a main body (12) defining a plurality of passageways (14) therein. A conductive strip (22) including a plurality of downward extending tangs (24) adapted to be received within the corresponding passageways (14), respectively, is attached to the main body (12) from the top. A cover (28) including a pair of locking tabs (30) positioned at two opposite ends, is fastened to the main housing (12) and has the conductive strip (22) sandwiched therebetween. An offset area (36) is formed on the top surface (26) of the main body (12) for snugly receiving the conductive strip (22) therein. Each of some passageways (14) further includes a guidable alignment post (15) for aligning and pre-loading the inserted tang (24) therewith.