Patents by Inventor Lee Shuang Wang
Lee Shuang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038612Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: October 16, 2023Publication date: February 1, 2024Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Patent number: 11876028Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: GrantFiled: October 15, 2021Date of Patent: January 16, 2024Assignee: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
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Publication number: 20230361009Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.Type: ApplicationFiled: May 9, 2023Publication date: November 9, 2023Applicant: Infineon Technologies AGInventors: Lee Shuang WANG, Marta ALOMAR DOMINGUEZ, Marcus BÖHM, Edward FÜRGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER
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Patent number: 11804424Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: GrantFiled: December 1, 2020Date of Patent: October 31, 2023Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Publication number: 20230298956Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.Type: ApplicationFiled: March 8, 2023Publication date: September 21, 2023Applicant: Infineon Technologies AGInventors: Chii Shang HONG, Li Fong CHONG, Yee Beng DARYL YEOW, Edward FÜRGUT, Mei Fen HIEW, Azlina KASSIM, Ralf OTREMBA, Bernd SCHMOELZER, Joon Shyan TAN, Lee Shuang WANG
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Patent number: 11676881Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.Type: GrantFiled: July 15, 2020Date of Patent: June 13, 2023Assignee: Infineon Technologies AGInventors: Ralf Otremba, Teck Sim Lee, Klaus Schiess, Xaver Schloegel, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Patent number: 11362023Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.Type: GrantFiled: July 12, 2019Date of Patent: June 14, 2022Assignee: Infineon Technologies AGInventors: Jayaganasan Narayanasamy, Meng How Chong, Elmer Senorin Holgado, Chee Ming Lam, Sanjay Kumar Murugan, Arivindran Navaretnasinggam, Kai Yang Tan, Lee Shuang Wang
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Patent number: 11355424Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.Type: GrantFiled: September 4, 2020Date of Patent: June 7, 2022Assignee: Infineon Technologies AGInventors: Ralf Otremba, Teck Sim Lee, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Patent number: 11348866Abstract: A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure.Type: GrantFiled: June 16, 2020Date of Patent: May 31, 2022Assignee: Infineon Technologies Austria AGInventors: Thai Kee Gan, Edward Fuergut, Teck Sim Lee, Lee Shuang Wang
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Publication number: 20220157682Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: October 15, 2021Publication date: May 19, 2022Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Publication number: 20220108949Abstract: One example of a semiconductor package includes a first die pad, a first die, a second die pad, and a second die. The first die pad includes a main portion and a U-shaped rail portion extending from the main portion. The first die is electrically coupled to the first die pad. The second die pad is proximate the U-shaped rail portion of the first die pad. The second die is electrically coupled to the second die pad. The second die includes a magnetic field sensor.Type: ApplicationFiled: October 7, 2020Publication date: April 7, 2022Applicant: Infineon Technologies AGInventors: Lee Shuang WANG, Thai Kee GAN, Teck Sim LEE
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Publication number: 20210391246Abstract: A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Inventors: Thai Kee Gan, Edward Fuergut, Teck Sim Lee, Lee Shuang Wang
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Publication number: 20210175157Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: ApplicationFiled: December 1, 2020Publication date: June 10, 2021Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Patent number: 11011456Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.Type: GrantFiled: July 2, 2019Date of Patent: May 18, 2021Assignee: Infineon Technologies AGInventors: Thai Kee Gan, Lee Shuang Wang, Jo Ean Joanna Chye
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Publication number: 20210074614Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.Type: ApplicationFiled: September 4, 2020Publication date: March 11, 2021Inventors: Ralf Otremba, Teck Sim Lee, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Publication number: 20210020539Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.Type: ApplicationFiled: July 15, 2020Publication date: January 21, 2021Applicant: Infineon Technologies AGInventors: Ralf Otremba, Teck Sim Lee, Klaus Schiess, Xaver Schloegel, Lee Shuang Wang, Mohd Hasrul Zulkifli
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Publication number: 20210013135Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.Type: ApplicationFiled: July 12, 2019Publication date: January 14, 2021Inventors: Jayaganasan Narayanasamy, Meng How Chong, Elmer Senorin Holgado, Chee Ming Lam, Sanjay Kumar Murugan, Arivindran Navaretnasinggam, Kai Yang Tan, Lee Shuang Wang
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Publication number: 20210005541Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.Type: ApplicationFiled: July 2, 2019Publication date: January 7, 2021Applicant: Infineon Technologies AGInventors: Thai Kee Gan, Lee Shuang Wang, Jo Ean Joanna Chye
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Patent number: 10840164Abstract: A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall.Type: GrantFiled: May 18, 2018Date of Patent: November 17, 2020Assignee: Infineon Technologies AGInventors: Chii Shang Hong, Edmund Sales Cabatbat, Lee Shuang Wang
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Publication number: 20190355643Abstract: A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall.Type: ApplicationFiled: May 18, 2018Publication date: November 21, 2019Inventors: Chii Shang Hong, Edmund Sales Cabatbat, Lee Shuang Wang