Patents by Inventor Lee Shuang Wang

Lee Shuang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204845
    Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
  • Patent number: 10147703
    Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
  • Publication number: 20180277513
    Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
  • Patent number: 9922910
    Abstract: An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant and being functionalized for promoting heat dissipation via the interface structure on a heat dissipation body.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Murugan, Lee Shuang Wang
  • Publication number: 20180061745
    Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.
    Type: Application
    Filed: August 28, 2017
    Publication date: March 1, 2018
    Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
  • Publication number: 20170098598
    Abstract: An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant and being functionalized for promoting heat dissipation via the interface structure on a heat dissipation body.
    Type: Application
    Filed: September 21, 2016
    Publication date: April 6, 2017
    Inventors: Ralf OTREMBA, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Nurugan, Lee Shuang Wang
  • Publication number: 20160365296
    Abstract: A device includes an encapsulation material and a first lead and a second lead protruding out of a surface of the encapsulation material. A recess extends into the surface of the encapsulation material. An elevation is arranged on the surface of the encapsulation material. The first lead protrudes out of the elevation.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 15, 2016
    Inventors: Ralf Otremba, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Murugan, Lee Shuang Wang