Abstract: The present invention provides compositions and methods for enhancing transport of biologically active compounds across biological membranes and across and into animal epithelial or endothelial tissues. The composition includes a biologically active agent and a transport moiety. The transport moiety includes a structure selected from the group consisting of (ZYZ)nZ, (ZY)nZ, (ZYY)nZ and (ZYYY)nZ. Subunit “Z” is L-arginine or D-arginine, and subunit “Y” is an amino acid that does not comprise an amidino or guanidino moiety. Subscript “n” is an integer ranging from 2 to 10. The method for enhancing transport involves the administration of the aforementioned composition.

Abstract: Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs utilizing communication over the specialized bus, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

Abstract: A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

Abstract: A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.

Abstract: A removable bird cup feeder assembly is comprised of a dish holder and a cup shaped dish. The dish holder has a slide rail, a vertical stop member, a horizontal stop member and a cage displacement member. The slide rail fits into a tunnel formed on the dish by a flange and a wall of the dish. The stop members limit horizontal and vertical movement of the dish. The fit between the flange and the slide rail limits rotation of the dish. The dish has an embossed floor, radiused floor and wall intersections, and radiused top wall surfaces to enhance bird comfort and to facilitate cleaning of the dish. The assembly is installed within a cage. When the cage door is opened, the dish may be quickly removed and replaced. When the cage door is closed the dish cannot be displaced by a bird within the cage.

Abstract: The present invention includes a system with a sensor to detect a change in one or more physical characteristics and provide a corresponding electrical sensor signal, a controller including a power source for the sensor, and transient suppression circuitry. This circuitry is coupled between the sensor and the power source of the controller, and includes a first thermistor to protect the sensor from a power surge from the controller and/or power source.

Abstract: A data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address.

Abstract: A method, system, and apparatus for placing and removing data elements into a bi-directionally growing first in last out data structure is provided. In one embodiment, in response to a request to place a data element into the data structure, a head pointer is advanced one memory location in a direction indicated by a state of a direction flag. The new data element is placed into the memory location indicated by the head pointer. The position of the head pointer and the base pointer are swapped in preparation for receiving a new data element and the state of the direction flag is reversed to indicate growth of the data structure in the opposite direction. In response to a request to remove a data element from the data structure, the head and base pointers are swapped and the state of the direction flag is reversed.

Abstract: A move engine and operating system transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. The operating system stores FROM and TO real addresses in unique fields in memory that are used to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the operating system stalls.

Abstract: A processor contains a move engine and a memory controller contains a mapping engine that, together, transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores current and new real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the current and new real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory modules. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: A processor contains a move engine and mapping engine that transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores FROM and TO real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the FROM and TO real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory module. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space.

Abstract: A data processing system having a physically addressed cache of disk memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.

Abstract: A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.