Abstract: A method is provided for producing a cathode active material. The method includes providing an anode sheet comprising an anode material disposed on an anode current collector and a cathode sheet comprising a cathode material disposed on a cathode current collector, delaminating the anode material from the anode current collector, separating the anode material from the anode current collector, and delaminating the cathode material from the cathode current collector. The method further includes performing size reduction and deagglomeration on the cathode material, which includes the cathode active material and a binder, separating the cathode material from the cathode current collector using a filter and/or a sieve, and performing gravity separation to separate the cathode active material from the binder.

Abstract: A vibration detector includes a housing, a cover plate, a piezoelectric sensing module, and a PCBA module. The piezoelectric sensing module is arranged in the housing and generates a piezoelectric signal in response to vibration of the cover plate. The PCBA module is arranged in the housing and is electrically coupled to the piezoelectric sensing module. The PCBA module is adapted to receive the piezoelectric signal from the piezoelectric sensing module and to generate a detection signal based on the piezoelectric signal.

Abstract: Disclosed herein are charge or electricity generating devices and methods of making and use thereof.

Abstract: A semiconductor device including a first transistor and a second transistor. The first transistor has a first body. The first body of the first transistor is connected to receive a first reference voltage. The second transistor has a second body. The second body of the second transistor is electrically disconnected from the first body of the first transistor. The first transistor and the second transistor are electrically connected in series.

Abstract: A system adapted to detect rotation of at least two spray arms of a household appliance spaced along a longitudinal axis of the appliance includes a first detection magnet, a second detection magnet and a magnetic sensor. The first detection magnet is arranged on a first spray arm of the at least two spray arms. The second detection magnet is arranged on a second spray arm of the at least two spray arms. A magnetic field direction of the second detection magnet is different from a magnetic field direction of the first detection magnet. The magnetic sensor is arranged in the household appliance and is adapted to sense a motion status of the first detection magnet and the second detection magnet.

Abstract: A sensor module comprises a housing and a liquid level sensing module. The housing includes a first passage adapted to permit liquid to flow into an interior of the housing. The first passage defines an air chamber and an air passage in communication with the air chamber. The liquid level sensing module is arranged in the interior of the housing, and includes at least a first part positioned within the air passage. The liquid level sensing module is adapted to sense a characteristic indicative of a liquid level when the liquid flows into the first passage and compresses air in the air passage.

Abstract: A turbine body includes a turbine rotor having a blade to rotate around an axis of rotation, and a housing including an inner wall surface surrounding the turbine rotor. During a rotation of the turbine rotor, a fluid is directed from a leading edge of the blade toward a trailing edge of the blade, and the blade is imparted with a first excitation force in response to the rotation of the turbine rotor. The inner wall surface has a plurality of grooves arranged along a circumferential direction that are positioned to intermittently face the trailing edge of the blade when the turbine rotor rotates, to generate a second excitation force that suppresses the first excitation force.

Abstract: An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

Abstract: A method is provided for removing a binder from a spent cathode active material. The method includes mixing the spent cathode active material with water to form a first mixture. The spent cathode active material includes cathode active material particles and the binder. The method further includes grinding the first mixture to separate the binder from the cathode active material particles, mixing the first mixture with a hydrocarbon liquid, agitating the hydrocarbon liquid and the first mixture and forming an oil phase and a water phase, and separating the oil phase from the water phase. The first mixture contains the cathode active material particles, the binder and the water. The oil phase contains the hydrocarbon liquid and the binder, and the water phase contains the cathode active material particles and the water.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes defining first through fourth PMOS transistors in an n-well region, arranging a plurality of conductive regions whereby a bias circuit is configured to include the first and second PMOS transistors and a level shifter is configured to include the third and fourth PMOS transistors, and arranging a plurality of conductive elements whereby a first power domain includes electrical connections to each of the first and third PMOS transistors and a second power domain includes electrical connections to each of the second and fourth PMOS transistors.

Abstract: A method is provided for producing a cathode active material. The method includes shredding an anode sheet including an anode material disposed on an anode current collector with a cathode sheet including a cathode material disposed on a cathode current collector, rinsing the sheets with an organic solvent, agitating the sheets to delaminate the anode material from the anode current collector, separating the anode material from the anode current collector using a filter and/or a sieve, and blending the anode current collector and the cathode sheet to delaminate the cathode material from the cathode current collector. The method further includes performing size reduction and deagglomeration on the cathode material, which includes the cathode active material and a binder, separating the cathode material from the cathode current collector using a filter and/or a sieve, and performing gravity separation to separate the cathode active material from the binder.

Abstract: A circuit includes a reference node configured to carry a reference voltage level, a pull-down driver coupled to the reference node, a first node configured to carry an input signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage, a voltage regulator configured to output a gate signal having a divided value of the input signal, a gate control circuit configured to output a first voltage level being a greater voltage level of the power supply voltage or the gate signal and output a second voltage level being a greater voltage level of the input signal or the first voltage level, and first and second transistors coupled in series between the first node and the pull-down driver and configured to receive the first and second voltage levels.

Abstract: Methods, systems, and devices for status indications for storing data to a memory system via command headers are described. The described techniques provide for a host system to utilize initiator identifier (IID) and extended IID (EXT_IID) fields of a write command to indicate storage information for storing data. The host system may indicate a host process via a first set of one or more bits of the storage information, which may support the memory system identifying a storage location for storing the data. Additionally, the host system may indicate a storage configuration via a second set of one or more bits of the storage information, which may support the memory system identifying a type of memory for storing the data. For example, the storage configuration may indicate whether the data is high performance data, high-stress data, hot or cold data, or any combination thereof.

Abstract: Various examples are provided related to dust particle removal in underground mining. In one example, a filter system for removing dust particles includes a mesh system comprising one or more meshes, a frame bed for holding the mesh system, and vibrational energy transfer from the continuous miner to the mesh system. In another example, a method for removing dust particles includes contacting the dust particles with the filter system mounted to the continuous miner, where the continuous miner produces vibrational energy sufficient to vibrate the mesh in the filter system.

Abstract: An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

Abstract: Exemplary methods, apparatuses, and systems include a performance mode manager for controlling performance of a wireless update by selecting a performance mode using rations of allocation. The performance mode manager receives a request to initialize a file transfer from a host using wireless communication. In response to the request, the performance mode manager identifies a size of the file transfer by the memory subsystem. The performance mode manager selects a performance mode from a plurality of performance modes and allocates the available set of memory pages using the performance mode. The performance mode manager receives a file of the file transfer. The performance mode manager programs a first portion of the file at the default bit density to the first portion of memory and a second portion of the file at the reduced bit density to the second portion of memory.

Abstract: A semiconductor device includes first and second transistors electrically connected in series, third and fourth transistors electrically connected in series, and first and second diodes. A body and a source of the first transistor are connected to a first reference node, and are electrically disconnected from a body of the second transistor. Gates of the first and second transistors are configured to receive a first control signal. Drains of the second and fourth transistors are connected to an input/output node. A body and a source of the third transistor are connected to a second reference node, and are electrically disconnected from a body of the fourth transistor. Gates of the third and fourth transistors are connected to receive a second control signal. The first diode is connected between the input/output node and the first reference node. The second diode is connected between the input/output node and the second reference node.

Abstract: A circuit includes a reference node having a reference voltage level, a first node that carries an input signal having a first voltage level or the reference voltage level, a second node that carries a power supply voltage, a voltage regulator including a source follower that outputs a gate signal having a fractional value of the input signal, a first control circuit that selects the higher of the power supply voltage or the gate signal as a first control signal, a second control circuit that selects the higher of the input signal or the first control signal as a second control signal, and first and second transistors coupled in series between the first node and the reference node and configured to receive the first and second control signals.

Abstract: Methods, systems, and devices for data handling during a reflow operation are described. The method may include a memory system receiving first signaling indicating that a reflow operation is to be performed on the memory system and determining whether an amount of data stored in a first set of memory cells within one or more memory devices of the memory system satisfy a threshold. The method may further include the memory system communicating an indication of whether the memory system is ready for the reflow operation based on the amount of data satisfying the threshold.

Abstract: An integrated circuit is provided. The integrated circuit comprises first active regions and second active regions. The first active regions are coupled between a pad and a first voltage terminal and configured to discharge electrostatic charges. A first region, which is the closest active region to the pad in the plurality of first active regions have a width greater than widths of remaining active regions in the plurality of first active regions. The first region is included in a first transistor having a breakdown voltage. The second active regions are coupled between the pad and the first voltage terminal. The second active regions are included in an electrostatic discharge primary circuit having a trigger voltage different from the breakdown voltage. The second active regions discharge the electrostatic charges in response to a first voltage between the pad and the first voltage terminal exceeding the trigger voltage.