Abstract: A semiconductor device including a first transistor and a second transistor. The first transistor has a first body. The first body of the first transistor is connected to receive a first reference voltage. The second transistor has a second body. The second body of the second transistor is electrically disconnected from the first body of the first transistor. The first transistor and the second transistor are electrically connected in series.

Abstract: An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

Abstract: An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

Abstract: The present disclosure concerns aluminum conductor alloys having increased creep resistance, aluminum products comprising same and process using same. In some embodiments, the aluminum conductor alloy comprises, in weight percent: up to about 0.10 Si; up to about 0.5 Fe; up to about 0.30 Cu; between about 0.02 and about 0.1 Mg; up to about 0.04 B; and the balance being aluminum and unavoidable impurities.

Abstract: A plug-in connector having terminal provided in terminal receiving cavities. The terminals have memory card engagement sections. A memory card receiving slot is provided in the housing. The memory card receiving slot spans the terminal receiving cavities. A portion of the memory card receiving slot is in alignment with each of the terminal receiving cavities. An elongated opening extends between the memory card receiving slot and the terminal receiving cavities. A memory card is positioned in the memory card receiving slot. The memory card stores data which is identifiable to the specific device and allows the data to be easily conveyed.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: A method is provided and includes the operation below: discharging electrostatic charges from a pad to a first voltage terminal through a first active region coupled to the pad and a second active region coupled between the first active region and the first voltage terminal, in which the first active region and the second active region are the same conductivity type and have different widths from each other, and the first active region and the second active region are included in a first transistor having a first breakdown voltage; and discharging the electrostatic charges through an ESD primary circuit having a first terminal coupled with the first active region and a second terminal coupled with the first voltage terminal. The ESD primary circuit has a trigger voltage lower than the first breakdown voltage.

Abstract: An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge(ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

Abstract: A circuit includes a bias circuit and a level shifter. The bias circuit includes first and second input terminals configured to receive first and second power supply voltages, and is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The level shifter includes a first PMOS transistor configured to receive the first power supply voltage and a second PMOS transistor configured to receive the second power supply voltage, and each of the first and second PMOS transistors includes a bulk terminal configured to receive the bias voltage.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: A vehicle image-taking device and a vehicle are provided, relating to the technical field of vehicles. The vehicle image-taking device includes an image-taking mechanism and a fixing mechanism. The fixing mechanism including a fixation portion and an installation portion, the installation portion is used for fixing the image-taking mechanism, and the fixation portion is provided thereon with a clamping member used for being clamped in a rubber strip of a vehicle. In the use process, the clamping member on the fixation portion is clamped in the rubber strip of a vehicle, so that the fixation portion is fixedly connected with the vehicle. Since the image-taking mechanism is fixed on the installation portion, the image-taking mechanism is then fixed on the vehicle. Such installation manner of clamping is simple to operate, does not damage or contaminate the vehicle body, and reduces the installation cost. In addition, the clamping member can cooperate with any rubber strip in the vehicle, i.e.

Abstract: An intelligent anti-icing material and a preparation method and use thereof are disclosed. The intelligent anti-icing material includes a hydrophobic resin and a nickel-titanium alloy wire embedded in the hydrophobic resin. When the surrounding temperature decreases, the hydrophobic resin in the intelligent anti-icing material shrinks, and the nickel-titanium alloy wire featured by thermoelastic martensitic transformation undergoes phase transformation and expands, which changes the direction of the expansion force inside the ice layer, and thus tiny cracks occur at the interface between the ice layer and the surface of the material, thereby reducing the adhesion of the ice layer to the surface of the material, accelerating the spontaneous shedding of the ice layer, without heating, and achieving an excellent anti-icing effect.

Abstract: An integrated circuit includes a pull-up circuit, an electrostatic discharge (ESD) primary circuit, and a pull-down circuit. The pull-up circuit is coupled between a pad and a first voltage terminal. The ESD primary circuit includes a first terminal which is coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal. The pull-down circuit has a first terminal which is coupled to the pad, the ESD primary circuit and the pull-up circuit, and a second terminal coupled to the second voltage terminal. The pull-down circuit includes at least one first transistor of a first conductivity type having a first terminal coupled to the first terminal of the pull-down circuit. A breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary circuit.

Abstract: A circuit includes a reference node having a reference voltage level, a first node that carries an input signal having a first voltage level or the reference voltage level, a second node that carries a power supply voltage, a voltage regulator including a source follower that outputs a gate signal having a fractional value of the input signal, a first control circuit that selects the higher of the power supply voltage or the gate signal as a first control signal, a second control circuit that selects the higher of the input signal or the first control signal as a second control signal, and first and second transistors coupled in series between the first node and the reference node and configured to receive the first and second control signals.

Abstract: An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.

Abstract: An integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node, and generates an initiation voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitive unit at the first node and coupled to a second capacitive unit at a second node. The first voltage generation circuit generates, in response to the initiation voltage at the first node, a first control signal based on a first supply voltage to the second voltage generation circuit. The second voltage generation circuit generates, in response to the first control signal received from the first voltage generation circuit, a second control signal to the first node, based on a second supply voltage.

Abstract: A rearview mirror having a display instrument function and a control system thereof are provided. The rearview mirror includes LED lights, glass and a glue-filled fluorophor located between the LED lights and the glass. Light rays emitted from the LED lights pass through the glue-filled fluorophor and are directed towards the glass. The glue-filled fluorophor includes a body and an extension portion, the body is flush with the LED lights, the extension portion is above the body and higher than the LED lights. Light-emitting areas are formed on outer surfaces of the body and the extension portion. The control system of the rearview mirror includes an OBD, an MCU and LED lights. The OBD is configured to acquire information on rpm and vehicle speed, and transmits it to the MCU. The MCU receives the information, generates control information and transmits it to a corresponding LED light for display.

Abstract: A simulation evaluation model of a high voltage ride through capability includes a wind turbine system aerodynamic model, a torque control model, a converter model, and a high voltage fault generating device model connected in sequence; the wind turbine system aerodynamic model is configured to calculate an airflow input power; the torque control model is configured to calculate a rotor electromagnetic torque according to the airflow input power; the high voltage fault generating device model is configured to simulate a high voltage fault and output a predetermined voltage on a low voltage side of a transformer; and the converter model is configured to calculate a stator reactive current, an active power and a reactive power of the wind turbine system during the high voltage fault according to the airflow input power, the rotor electromagnetic torque and the predetermined voltage on the low voltage side of the transformer.

Abstract: An electrical connection assembly includes a circuit board and a connector mounted on the circuit board. The connector has a housing and a contact received in the housing. The contact has an elastic arm extending out from a surface of the housing and a connection pin extending out from a side face of the housing. The elastic arm electrically contacts an electrical contact pad on a moving bracket and the connection pin electrically contacts the circuit board.

Abstract: The present invention provides a series compensator and a control method. The series compensator includes a series transformer, a series transformer bypass device, a voltage source converter, a high-speed converter bypass device, a high-speed switch, and a reactor. The reactor and the high-speed switch are connected in parallel to form a current limiting module; one winding of the series transformer has two ends connected in series to a line, and the other winding thereof is sequentially connected to the current limiting module and the high-speed converter bypass device; the voltage source converter and the high-speed converter bypass device are connected in parallel; and at least one winding of the series transformer are connected in parallel to at least one series transformer bypass device.