Abstract: An IC structure includes first and second gates, first and second source regions, a shared drain region, and an isolation region. The first gate has a first portion extending along a first direction and a second portion extending along a second direction. The second gate has a first portion extending along the first direction and a second portion extending along the second direction. The shared drain region extends from the first portion of the first gate to the first portion of the second gate. The first source region is spaced apart from the shared drain region by the first gate. The second source region is spaced apart from the shared drain region by the second gate. The isolation region is between the first portion of the first gate and the first portion of the second gate, and resembles a quadrilateral pattern bordering the shared drain region.

Abstract: An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

Abstract: Methods, systems, and devices for external power functionality techniques for memory devices are described. A memory system, which may be coupled to a first power source associated with a first voltage, may detect whether a second power source associated with a second voltage higher than the first voltage is available. The memory device may activate a functionality to use the second power source for the access operations if the second power source is available, and the memory device may then perform one or more access operations using the second voltage from the second power source based on the activated functionality.

Abstract: An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

Abstract: Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Abstract: The disclosure provides a micro control device for simulating the electric thermal field change of a plate/strip, comprising a plate shape simulating test platform, a high current regulating power supply, a current regulating device, a thermal imager, a thermocouple, a non-contact type full field strain gauge, a high-power current control device and an electro-plastic control system; for a plate/strip with large width to thickness ratio and high hardness and brittleness alloy, different numbers of electrodes are arranged laterally along the movable supporting beam. A high-power current control device is used to realize the sub-regional control of the electric field, thermal field and stress field of the plate/strip; at the same time, the movable supporting beam and tension sensor are used to test the working conditions of the plate/strips with different lengths and widths, to simulate the instantaneous synchronous entanglement process between different fields.

Abstract: An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.

Abstract: A circuit includes an input circuit, a level shifter circuit and an output circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second input signal or the third input signal. The level shifter circuit includes a header circuit coupled to a first node, and is configured to enable or disable the level shifter circuit responsive to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and is configured to generate an output signal.

Abstract: Provided are a method and an apparatus for implementing a call service, an electronic device, and a computer readable storage medium, the method includes: deciding whether a first state of a terminal in an eMSC is consistent with a second state of the terminal in an IMS; if they are inconsistent, sending a registration request to the IMS to cause the terminal to complete an initial call service, wherein the eMSC does not subscribe to registration state information in the IMS.

Abstract: An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

Abstract: In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is smaller than the first changing rate.

Abstract: An integrated circuit includes a middle active-region structure between a group-one active-region structure and a group-two active-region structure. The integrated circuit also includes a main circuit, a group-one circuit, and a group-two circuit. The main circuit includes at least one boundary gate-conductor intersecting the middle active-region structure. The group-one circuit includes a group-one isolation structure separating the group-one active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit. The group-two circuit includes a group-two isolation structure separating the group-two active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit.

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: Disclosed herein are charge or electricity generating devices and methods of making and use thereof.

Abstract: The present disclosure discloses a method for modulating a switch of a converter. The method is applicable to a topological structure of a multiphase stacked interleaved buck converter, and includes: acquiring charge-discharge state information in the topological structure, wherein the charge-discharge state information comprises at least a first charge-discharge state of any one phase primary loop, a second charge-discharge state of a secondary loop corresponding to the any one phase primary loop, a third charge-discharge state of another primary loop, and a fourth charge-discharge state of another secondary loop; and adjusting, based on the first charge-discharge state, a closed state of a switch disposed on a bridge arm connected to the any one phase primary loop, and adjusting, based on the second charge-discharge state and the third charge-discharge state, a closed state of a switch disposed on another bridge arm.

Abstract: Provided is a method for feature extraction of a remote sensing image based on tensor collaborative graph discriminant analysis, including: taking each of pixels as a center for intercepting a three-dimensional tensor data block; dividing experimental data into a training set and a test set in proportion; computing a Euclidean distance between a current training pixel and each class of training data; configuring a L2 norm collaborative representation model with a weight constraint; acquiring a projection matrix of each dimension of each of the three-dimensional tensor data block; and utilizing a low-dimensional projection matrix to obtain a training set and a test set, expanding the training set and the test set into a form of column vectors according to a feature dimension, inputting extracted low-dimensional features into a support vector machine classifier for classification, to determine a class of the test set, and evaluating, by a classification effect, performance of feature extraction.

Abstract: Methods, systems, and devices for external power functionality techniques for memory devices are described. A memory system, which may be coupled to a first power source associated with a first voltage, may detect whether a second power source associated with a second voltage higher than the first voltage is available. The memory device may activate a functionality to use the second power source for the access operations if the second power source is available, and the memory device may then perform one or more access operations using the second voltage from the second power source based on the activated functionality.

Abstract: An integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node, and generates an initiation voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitive unit at the first node and coupled to a second capacitive unit at a second node. The first voltage generation circuit generates, in response to the initiation voltage at the first node, a first control signal based on a first supply voltage to the second voltage generation circuit. The second voltage generation circuit generates, in response to the first control signal received from the first voltage generation circuit, a second control signal to the first node, based on a second supply voltage.