Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.

Abstract: A dynamic logic circuit includes a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal. A second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal.

Abstract: Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.

Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

Abstract: A voltage conversion circuit such as a buck regulator circuit has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches. The voltage conversion circuit can also include means to reduce or cancel a detrimental effect of other wires on same chip, such as a power grid, that conduct a return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.

Abstract: A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.

Abstract: A dynamic logic circuit includes a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal. A second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal.

Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.

Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

Abstract: A method for increasing performance in a limited switch dynamic logic (LSDL) circuit includes precharging a dynamic node during a precharge phase of a first and second evaluation clock signal. The dynamic node is evaluated to a first logic value in response to one or more first input signals of a first evaluation tree during an evaluation phase of the first evaluation clock signal. The dynamic node is evaluated to a second logic value in response one or more second input signals of a second evaluation tree during an evaluation phase of the second evaluation clock signal. A signal of the LSDL circuit is outputted in response to the dynamic node according to an output latch clock signal.

Abstract: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).

Abstract: A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a drain region are formed within a first region and a second region, respectively, of the pFET portion of the semiconductor layer including embedded silicon germanium (eSiGe). A source region and a drain region are formed within a first region and a second region, respectively, of the nFET portion of the semiconductor layer including eSiGe. The source and drain regions within the pFET portion includes at least one dimension that is different from at least one dimension of the source and drain regions within the nFET portion.

Abstract: A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.