Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Abstract: A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface of the flex circuitry. The semiconductor die is disposed beneath the leaded package IC and, in preferred embodiments, disposed in a window that passes through at least a part of the flex circuitry and is attached to a conductive layer of the flex circuitry. In other embodiments, the semiconductor die is attached to the body of the leaded packaged IC. The flex circuitry preferably employs at least two conductive layers and, in preferred embodiments, the leaded packaged IC is connected to the flex circuitry at one layer while the semiconductor die is connected to the flex circuitry at the other conductive layer.

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.

Abstract: A system and method for combining at least two semiconductor die using multi-layer flex circuitry is provided. A first semiconductor die is attached and preferably electrically connected to a first layer of the flex circuitry while a second semiconductor die is set, at least in part, into a window that extends into the flex circuitry to expose a layer of the flex to which the second die is attached. When the second semiconductor die is a flip-chip device, it is connected through its contacts to the layer of flex exposed in the window and when it is a die with its contact side oriented away from the flex circuitry, it is preferably electrically connected with wire bonds to another conductive layer of the flex circuitry. In preferred modules, the first semiconductor die is preferably a flash memory circuit and the second semiconductor die is preferably a controller.

Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along one side of a flex circuit. The semiconductor die is disposed along the flex circuitry and preferably is between at least a part of the flex circuitry and the body of the leaded packaged IC. Preferably, the die is attached to a conductive layer of the flex circuitry. The flex circuitry preferably employs at least two conductive layers and the leaded packaged IC and die are preferably connected to one of the conductive layers of the flex circuitry. In preferred modules, the leaded packaged IC is preferably a flash memory device and the semiconductor die is preferably a controller.

Abstract: Turbulence inducers are provided on circuit modules. Rising above a substrate or heat spreader surface, turbulence generators may be added to existing modules or integrated into substrates or heat spreaders employed by circuit modules constructed according to traditional or new technologies.

Abstract: A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system connects to a target interface for that kind of processor. That target interface then communicates with an emulator dynamic loader on the host computer connected to an emulator. The target interface communicates with the dynamic loader on the host computer to determine if there is support for the desired kind on the emulator. If not a target interface is loaded to the emulator and connected to the already running software on the host. A connection to this target interface software on the emulator is then provided to the host computer.

Abstract: The present invention provides a method for far branch and call instructions. The present invention includes the link-time modification of object code generated by the compiler or assembler and the addition of custom generated object code to the link for the purpose of implementing far branches and calls without changing the compiler generated instructions or expanding compiler generated object code.

Abstract: The present invention provides a visual linker. The visual linker includes a link server that implements linking instructions for sections to a memory. The visual linker also includes a graphical user interface that receives said instructions and displays said sections within said memory. The visual linker also includes an application programming interface that receives said instructions and reports the results of said linking instruction and said sections within said memory. The visual linker also includes an incomplete link comprising sections not allocated to said memory. The visual linker also includes a link recipe comprising said instructions implemented by said link server.

Abstract: A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfers the data from the emulator to the first device driver.

Abstract: A collection of program instructions capable of executing on a host processor suitable for reading from a memory location of a target processor and suitable for creating a real-time data channel between said host and target processors.

Abstract: A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system connects to a target interface for that kind of processor . That target interface then communicates with an emulator dynamic loader on the host computer connected to an emulator. The target interface communicates with the dynamic loader on the host computer to determine if there is support for the desired kind on the emulator. If not a target interface is loaded to the emulator and connected to the already running software on the host. A connection to this target interface software on the emulator is then provided to the host computer.

Abstract: A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfer the data from the emulator to the first device driver.

Abstract: A system for allocating code sections to a plurality of processors is provided. The system includes a linker for allocating and linking the code sections. The system also includes at least one private memory on each of the plurality of processors. The system also includes at least one shared memory accessible by the plurality of processors. The system also includes at least one incomplete link corresponding to the code sections not allocated to the at least one shared memory and the at least one private memory.