Patents by Inventor Leng Tan

Leng Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7747606
    Abstract: A method for receiving a database query language statement and performance information about the statement at an optimizer and generating one or more tuning actions for the statement with the performance information is disclosed.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: June 29, 2010
    Assignee: Oracle International Corporation
    Inventors: Benoit Dageville, Mohamed Ziauddin, Khaled Yagoub, Mohamed Zait, Dinesh Das, Karl Dias, Mark Ramacher, Leng Leng Tan
  • Patent number: 7727041
    Abstract: A light emitting device having a die that includes a light source that generates light of a first wavelength and a layer of phosphor particles covering the die is disclosed. The phosphor particles convert a portion of the light of the first wavelength to light of a second wavelength. The light source can be fabricated by attaching the light source to a substrate, and converting the light source by applying a light converting layer that includes a volatile carrier material and particles of a phosphor that convert light of the first wavelength to light of the second wavelength over the light source. The volatile carrier material is then caused to evaporate leaving a layer of the phosphor particles over the light source. A binder material can be incorporated in the volatile carrier for binding the phosphor particles to one another after the volatile carrier material is evaporated.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: June 1, 2010
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Kee Yean Ng, Kheng Leng Tan, Wen Ya Ou
  • Publication number: 20100059831
    Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
    Type: Application
    Filed: November 6, 2009
    Publication date: March 11, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
  • Patent number: 7664798
    Abstract: Systems and methods to define and store performance baselines. A baseline may be defined as a pair of snapshots, each snapshot containing the same set of statistics and having a timestamp value associated therewith. The present invention allows for the designation, automatically or manually, of statistics collected over a certain period of time to be stored and used for comparison. Baselines may be used, for example, to manually or automatically compare with current system performance, compare difference-difference values and set thresholds to monitor current system performance.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: February 16, 2010
    Assignee: Oracle International Corporation
    Inventors: Graham Stephen Wood, Alex Tsukerman, Richard Sarwal, Gary Ngai, Mark Ramacher, Leng Leng Tan
  • Patent number: 7615427
    Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: November 10, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
  • Patent number: 7547583
    Abstract: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: June 16, 2009
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Kee Yean Ng, Hui Peng Koay, Chiau Jin Lee, Kheng Leng Tan, Wei Liam Loo, Keat Chuan Ng, Aizar Abdul Karim Norfidathul
  • Publication number: 20090129085
    Abstract: An exemplary embodiment of an optical device may include a lead frame with a plurality of leads and a reflector housing formed around the lead frame. The reflector housing includes a first end face and a second end face and a peripheral sidewall extending between the first end face and the second end face. The reflector housing includes a first pocket with a pocket opening in the first end face and a second pocket with a pocket opening in the second end face. At least one LED die is mounted in the first pocket of the reflector housing, and a light transmitting encapsulant is disposed in the first pocket and encapsulating the at least one LED die.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Applicant: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
    Inventors: Abdul Karim Norfidathul Aizar, Chiau Jin Lee, Keat Chuan Ng, Kiam Soon Ong, Kheng Leng Tan
  • Patent number: 7524087
    Abstract: An exemplary embodiment of an optical device may include a lead frame with a plurality of leads and a reflector housing formed around the lead frame. The reflector housing includes a first end face and a second end face and a peripheral sidewall extending between the first end face and the second end face. The reflector housing includes a first pocket with a pocket opening in the first end face and a second pocket with a pocket opening in the second end face. At least one LED die is mounted in the first pocket of the reflector housing, and a light transmitting encapsulant is disposed in the first pocket and encapsulating the at least one LED die.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: April 28, 2009
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Abdul Karim Norfidathul Aizar, Chiau Jin Lee, Keat Chuan Ng, Kiam Soon Ong, Kheng Leng Tan
  • Patent number: 7526508
    Abstract: An intelligent database infrastructure wherein the management of all database components is performed by and within the database itself by integrating management of various components with a central management control. Each individual database component, as well as the central management control, is self-managing. A central management control module integrates and interacts with the various database components. The database is configured to automatically tune to varying workloads and configurations, correct or alert about bad conditions, and advise on ways to improve overall system performance.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: April 28, 2009
    Assignee: Oracle International Corporation
    Inventors: Leng Leng Tan, Gianfranco Putzolu, Richard Sarwal, Alex Tsukerman, Gary C. Ngai, Graham Stephen Wood, Karl Dias, Mark Ramacher, Benoit Dageville, Mohamed Ziauddin, Tirthankar Lahiri, Sujatha Muthulingam, Vishwanath Karra, Francisco Sanchez, Hsiao-Te Su, Wanli Yang, Vasudha Krishnaswamy, Sushil Kumar
  • Publication number: 20090106278
    Abstract: A diagnosability system for automatically collecting, storing, communicating, and analyzing diagnostic data for one or more monitored systems. The diagnosability system comprises several components configured for the collection, storage, communication, and analysis of diagnostic data for a condition detected in monitored system. The diagnosability system enables targeted dumping of diagnostic data so that only diagnostic data that is relevant for diagnosing the condition detected in the monitored system is collected and stored. This in turn enables first failure analysis thereby reducing the time needed to resolve the condition detected in the monitored system.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 23, 2009
    Applicant: Oracle International Corporation
    Inventors: Mark Ramacher, Gary Ngai, Benoit Dageville, Karl Dias, Yair Sarig, Marcus Fallen, Ajith Kumar Mysorenagarajarao, John Beresniewicz, Mike Feng, Jonathan Klein, Hailing Yu, Leng Tan, Balasubrahmanyam Kuchibhotla, Uri Shaft, Venkateshwaran Venkataramani, Amir Valiani
  • Publication number: 20090106180
    Abstract: Techniques for indicating the status or health of a software system in a simple and summarized manner. In one embodiment, a health meter is displayed that displays a status value indicating the status or health of the software system. The status or health of the system as indicated by the health meter may be based upon one or more characteristics or perspectives (or components) of the system, such as performance, resource utilization, reliability, availability, scalability, and status values computed for the components.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 23, 2009
    Applicant: Oracle International Corporation
    Inventors: Balasubrahmanyam Kuchibhotla, Karl Dias, Jonathan Klein, Gary Ngai, Mark Ramacher, Leng Tan
  • Publication number: 20090057708
    Abstract: A light source and method for making the same are disclosed. The light source includes a substrate, a die, and a cup. The substrate has a plurality of electrical traces thereon and the die includes an LED that is connected to two of the traces. The cup overlies the substrate and is filled with an encapsulant material. The die is located within the cup and is encapsulated by the substrate and the encapsulant material. The cup and encapsulant material have substantially the same coefficient of thermal expansion. The cup can include reflective sidewalls positioned to reflect light leaving the die. The cup, encapsulant and substrate can be constructed from the same material.
    Type: Application
    Filed: August 27, 2007
    Publication date: March 5, 2009
    Inventors: Norfidathul Aizar Abdul Karim, Siew It Pang, Kheng Leng Tan, Tong Fatt Chew
  • Publication number: 20090026549
    Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
    Type: Application
    Filed: September 30, 2008
    Publication date: January 29, 2009
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Young Way TEH, Yong Meng LEE, Chung Woh LAI, Wenhe LIN, Khee Yong LIM, Wee Leng TAN, John SUDIJONO, Hui Peng KOH, Liang Choo HSIA
  • Patent number: 7481562
    Abstract: A device and method for providing illuminating light utilizes quantum dots to convert at least some of the original light emitted from a light source of the device to longer wavelength light to change the color characteristics of the illuminating light. The quantum dots may be included in the light source, a light panel and/or an optional interface medium of the device.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: January 27, 2009
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Janet Bee Yin Chua, Kok Chin Pan, Kee Yean Ng, Kheng Leng Tan, Tajul Arosh Baroky
  • Publication number: 20080315317
    Abstract: A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Khee Yong Lim, Young Way Teh, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang-Choo Hsia
  • Patent number: 7445978
    Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: November 4, 2008
    Assignee: Chartered Semiconductor Manufacturing, Ltd
    Inventors: Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, John Sudijono, Hui Peng Koh, Liang Choo Hsia
  • Publication number: 20080170391
    Abstract: A light source having a lead frame, a body, and a plurality of dies, each die having an LED thereon is disclosed. The body includes a top surface, a bottom surface and a plurality of side surfaces. The lead frame includes first, second, and third sections, the first section includes a die mounting area having a first protrusion that passes through the body and terminates in a pad on the bottom surface. The second and third sections each include a protrusion that is bent to form first and second leads that run along one of the side surfaces. Each die is bonded to the die mounting area such that a first contact is electrically connected to the die mounting area, and a second contact is connected to one of the second and third sections. The first protrusion of the first section provides improved heat transfer.
    Type: Application
    Filed: January 12, 2007
    Publication date: July 17, 2008
    Inventors: Aizar Abdul Karim Norfidathul, Chiau Jin Lee, Kheng Leng Tan, Keat Chuan Ng, Kiam Soon Ong
  • Publication number: 20080153190
    Abstract: A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.
    Type: Application
    Filed: March 7, 2008
    Publication date: June 26, 2008
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventors: Kee Yean Ng, Hui Peng Koay, Chiau Jin Lee, Kheng Leng Tan, Wei Liam Loo, Keat Chuan Ng, Aizar Abdul Karim Norfidathul
  • Publication number: 20080144322
    Abstract: A light source having a rigid substrate, a first LED, and a flexible reflector housing is disclosed. The rigid substrate has a first surface having a plurality of electrical traces formed thereon, the first LED die being disposed on the first surface and connected to two of the electrical traces. The rigid substrate also includes a plurality of external electrical connections for accessing the electrical traces. The reflector housing includes a layer of flexible material having at least one cavity extending through the layer of flexible material. The layer of flexible material is bonded to the first surface such that the cavity overlies the first LED die. The cavity has walls that reflect light generated in the first LED die. The first die can be encapsulated in a layer of silicone encapsulant. The reflector can likewise be constructed from silicone.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 19, 2008
    Inventors: Aizar Abdul Karim Norfidathul, Siew It Pang, Kheng Leng Tan, Tong Fatt Chew
  • Patent number: D576966
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: September 16, 2008
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd.
    Inventors: Keat Chuan Ng, Chiau Jin Lee, Kheng Leng Tan, Wei Liam Loo