Abstract: An analog-to-digital converter (ADC) has been disclosed. In some implementations, the ADC is configured to generate ADC samples based on input signals and an ADC input clock. The ADC is further configured to generate at a first time point a synchronized start signal indicating a starting point of capturing the ADC samples. The start signal and a system clock can be synchronized at a second time point. At a third time point, a capturing sample clock for capturing the ADC samples is generated. The synchronized start signal and the capturing sample clock can be input to a counter to determine a time difference between the second and third time points. An ADC output timing of the ADC samples can be determined based on the time difference.

Abstract: According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: According to embodiments, an example UE may include means for obtaining a set of ADC samples generated by an ADC based on analog signals and an ADC input clock and means for generating, at a first time point, a start signal indicating a starting point of capturing the set of ADC samples. The UE may also include means for synchronizing, at a second time point, the start signal and a system clock and means for generating, at a third time point, a capturing sample clock for capturing the set of ADC samples. The means may further include means for inputting the start signal and the capturing sample clock to a counter to determine a time difference between the second time point and the third time point and means for determining the ADC output timing of the set of ADC samples based on the time difference.

Abstract: According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.

Abstract: A delay cell for a delay locked loop, DLL, based serial link is disclosed. The delay cell has a first stage and a second stage, wherein an output of the first stage is an input to the second stage, the first stage comprising a resistive digital to analog converter, R-DAC and the second stage comprising a current starved delay cell.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: Various aspects of the present disclosure generally relate to control of a user device under a wet condition. In some aspects, a user device may determine whether the user device is operating under a wet condition; select, based at least in part on whether the user device is operating under the wet condition, a set of input components to control the user device, wherein the set of input components is selected from a plurality of different sets of input components; and configure a user interface of the user device according to the set of input components. Numerous other aspects are provided.

Abstract: Various aspects of the present disclosure generally relate to control of a user device under a wet condition. In some aspects, a user device may determine whether the user device is operating under a wet condition; select, based at least in part on whether the user device is operating under the wet condition, a set of input components to control the user device, wherein the set of input components is selected from a plurality of different sets of input components; and configure a user interface of the user device according to the set of input components. Numerous other aspects are provided.

Abstract: Various aspects of the present disclosure generally relate to control of a user device under a wet condition. In some aspects, a user device may determine whether the user device is operating under a wet condition; select, based at least in part on whether the user device is operating under the wet condition, a set of input components to control the user device, wherein the set of input components is selected from a plurality of different sets of input components; and configure a user interface of the user device according to the set of input components. Numerous other aspects are provided.

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Abstract: Various aspects of the present disclosure generally relate to control of a user device under a wet condition. In some aspects, a user device may determine whether the user device is operating under a wet condition; select, based at least in part on whether the user device is operating under the wet condition, a set of input components to control the user device, wherein the set of input components is selected from a plurality of different sets of input components; and configure a user interface of the user device according to the set of input components. Numerous other aspects are provided.

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Abstract: Various features relate to a test ring including an integrated circuit. The test ring is located around a periphery of the integrated circuit. The test ring includes a first terminal, a second terminal, and a first circuit element, wherein the first terminal is coupled to the first circuit element, and the first circuit element is coupled to the second terminal, wherein the first terminal, the first circuit element and the second terminal are coupled together in series.

Abstract: An apparatus includes an integrated circuit configured to be operatively coupled to a sensor array that is configured to generate an ultrasonic wave. The integrated circuit includes a transmitter circuit configured to provide a first signal to the sensor array. The integrated circuit further includes a receiver circuit configured to receive a second signal from the sensor array in response to providing the first signal. The sensor array includes an ultrasonic transmitter configured to generate the ultrasonic wave in response to the first signal and a piezoelectric receiver layer configured to detect a reflection of the ultrasonic wave.

Abstract: Apparatus and method for generating a DC pixel voltage are disclosed. The apparatus includes an amplifier configured to amplify an input signal to generate a voltage signal, wherein the input signal is generated in response to an ultrasonic wave reflecting off an item-to-be-imaged and propagating via a piezoelectric layer; a noise reduction circuit configured to pass the voltage signal from an output of the amplifier to a node, while reducing a propagation of noise from the output of the amplifier to the node; and a circuit configured to generate a DC pixel voltage based on the reduced-noise voltage signal.

Abstract: Apparatus and method for generating a DC pixel voltage are disclosed. The apparatus includes an amplifier configured to amplify an input signal to generate a voltage signal, wherein the input signal is generated in response to an ultrasonic wave reflecting off an item-to-be-imaged and propagating via a piezoelectric layer; a noise reduction circuit configured to pass the voltage signal from an output of the amplifier to a node, while reducing a propagation of noise from the output of the amplifier to the node; and a circuit configured to generate a DC pixel voltage based on the reduced-noise voltage signal.

Abstract: An apparatus, such as a pixel sensor for an ultrasonic imaging apparatus, is disclosed. The apparatus includes a first metallization layer coupled to a piezoelectric layer, wherein a first voltage is formed at the first metallization layer in response to an ultrasonic wave reflecting off an item-to-be-imaged (e.g., a user's fingerprint) and propagating through the piezoelectric layer, and wherein the first metallization layer is situated above a substrate; a second metallization layer situated between the first metallization layer and the substrate; and a device configured to apply a second voltage to the second metallization layer to reduce a parasitic capacitance between the first metallization layer and the substrate.

Abstract: A method of operation of an ultrasonic sensor array includes receiving a receiver bias voltage at a receiver bias electrode of the ultrasonic sensor array to bias piezoelectric sensor elements of the ultrasonic sensor array. The method further includes receiving a transmitter control signal at the ultrasonic sensor array to cause an ultrasonic transmitter of the ultrasonic sensor array to generate an ultrasonic wave. The method further includes generating data samples based on a reflection of the ultrasonic wave. The receiver bias voltage and the transmitter control signal are received from an integrated circuit that is coupled to the ultrasonic sensor array.