Abstract: Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described.

Abstract: Techniques for reducing ringing arising from L-C coupling in a boost converter circuit during a transition from a boost ON state to a boost OFF state. In an aspect, during an OFF state of the boost converter circuit, the size of the high-side switch coupling a boost inductor to the load is gradually increased over time. In this manner, the on-resistance of the high-side switch is decreased from a first value to a second (lower) value over time, which advantageously reduces ringing (due to high quality factor or Q) when initially entering the OFF state, while maintaining low conduction losses during the remainder of the OFF state. Further techniques are provided for implementing the high-side switch as a plurality of parallel-coupled transistors.

Abstract: Techniques for providing negative current information to a control loop for a buck converter in reverse boost mode. In an aspect, negative as well as positive current through an inductor is sensed and provided to adjust a ramp voltage in the control loop for the buck converter. The techniques may prevent current through the inductor during reverse boost mode from becoming increasingly negative without bound; the techniques thereby reduce settling times when the target output voltage is reduced from a first level to a second level. In an aspect, the negative current sensing may be provided by sensing negative current through a charging, or PMOS, switch of the buck converter. The sensed negative current may be subtracted from a current used to generate the ramp voltage.

Abstract: Techniques for preventing reverse current in applications wherein a tracking supply voltage is placed in parallel with a switching power stage. The tracking supply voltage may be boosted to a level higher than a battery supply voltage using, e.g., a boost converter. In an aspect, a negative current detection block is provided to detect negative current flow from the boosted tracking supply voltage to the battery supply voltage. A high-side switch of the switching power stage may be disabled in response to detecting the negative current. To prevent false tripping, the tracking supply voltage may be further compared with the battery supply voltage, and a latch may be provided to further control the high-side switch.

Abstract: Techniques for creating one or more notch frequencies in the power density spectrum of an output voltage generated by switching circuitry. In an aspect, high- and low-side switches are coupled to an output voltage via an inductor. The spectral power of the output voltage at one or more frequencies is estimated, and the estimated spectral power is provided to a switch controller controlling the switches. The switch controller may be configured to switch the switches only in response to detecting that the estimated spectral power at the notch frequency is at a minimum. In certain exemplary aspects, the techniques may be incorporated in an envelope-tracking system, wherein the switching circuitry forms part of a switched-mode power supply (SMPS) supplying low-frequency power to a power amplifier load.

Abstract: Techniques for dynamically generating a headroom voltage for an envelope tracking system. In an aspect, an initial headroom voltage is updated when a signal from a power amplifier (PA) indicates that the PA headroom is insufficient. The initial headroom voltage may be updated to an operating headroom voltage that includes the initial voltage plus a deficiency voltage plus a margin. In this manner, the operating headroom voltage may be dynamically selected to minimize power consumption while still ensuring that the PA is linear. In a further aspect, a specific exemplary embodiment of a headroom voltage generator using a counter is described.

Abstract: Techniques for generating a boost clock signal for a boost converter from a buck converter clock signal, wherein the boost clock signal has a limited frequency range. In an aspect, the boost clock signal has a maximum frequency determined by Vbst/T, wherein Vbst represents the difference between a target output voltage and a battery voltage, and T represents a predetermined cycle duration. The boost converter may include a pulse insertion block to limit the minimum frequency of the boost clock signal, and a dynamic blanking/delay block to limit the maximum frequency of the boost clock signal. Further techniques are disclosed for generally implementing the minimum frequency limiting and maximum frequency limiting blocks.

Abstract: Techniques for controlling boost converter operation in an envelope tracking (ET) system. In an aspect, an enable generation block is provided to generate an enable signal for a boost converter, wherein the enable signal is turned on in response to detecting that a sum of a first headroom voltage and an enable peak of a tracking supply voltage is greater than an amplifier supply voltage of the ET system. The enable signal may be turned on for a predetermined enable on duration. In another aspect, a target generation block is provided to generate a target voltage for the boost converter, wherein the target voltage comprises the sum of a second headroom voltage and a target peak of the tracking supply voltage.

Abstract: Techniques for controlling boost converter operation in an envelope tracking (ET) system. In an aspect, an enable generation block is provided to generate an enable signal for a boost converter, wherein the enable signal is turned on in response to detecting that a sum of a first headroom voltage and an enable peak of a tracking supply voltage is greater than an amplifier supply voltage of the ET system. The enable signal may be turned on for a predetermined enable on duration. In another aspect, a target generation block is provided to generate a target voltage for the boost converter, wherein the target voltage comprises the sum of a second headroom voltage and a target peak of the tracking supply voltage.

Abstract: Simple and efficient techniques for closed loop control of a boost converter. In an aspect, a current feed-forward (CFF) mode of operation includes providing current information to a control logic block controlling transistor switches of the boost converter to advantageously smooth the signals present in the closed loop control of the system. In another aspect, a modified peak current (MPC) mode of operation includes providing a simplified control mechanism based on a peak current mode of operation. Both CFF mode and MPC mode may share similar circuit elements, allowing a single implementation to selectively implement either of these modes of control. Further techniques are provided for determining average current information for the logic block.

Abstract: An adaptive gate drive circuit that can generate a gate bias voltage with temperature compensation for a MOSFET is disclosed. The adaptive gate drive circuit may generate the gate bias voltage with variable drive capability to combat higher gate leakage current of the MOSFET at higher temperature. In one design, an apparatus includes a control circuit and a gate drive circuit. The control circuit generates at least one control signal having a variable frequency determined based on a sensed temperature of the MOSFET. For example, a clock divider ratio may be determined based on the sensed temperature of the MOSFET, an input clock signal may be divided based on the clock divider ratio to obtain a variable clock signal, and the control signal(s) may be generated based on the variable clock signal. The gate drive circuit generates a bias voltage for the MOSFET based on the control signal(s).

Abstract: Techniques for performing noise cancellation/attenuation are disclosed. In one design, an apparatus includes a power supply generator having a switcher, a coupling circuit, an envelope amplifier, and a feedback circuit. The switcher generates DC and low frequency components and the envelope amplifier generates high frequency components of a supply voltage for a load, e.g., a power amplifier. The switcher receives a first supply voltage and provides a switcher output signal having switcher noise. The coupling circuit receives the switcher output signal and provides a first output signal having a first version of the switcher noise. The feedback circuit receives the switcher output signal and provides a feedback signal. The envelope amplifier receives an envelope signal and the feedback signal and provides a second output signal having a second version of the switcher noise, which is used to attenuate the first version of the switcher noise at the load.

Abstract: A noise cancellation circuit and quadrature downconverter for used in conjunction with a bandpass receiver. The noise cancellation uses at least one bandpass decimator and a summer. The output from each loop of a sigma-delta analog-to-digital converter (&tgr;&Dgr; ADC) is provided to a respective bandpass decimator. Each bandpass decimator uses an error cancellation filter, a bandpass filter, and a decimator. The transfer functions of the error cancellation filter and bandpass filter are convolved to provide the transfer function of the bandpass decimator. The filtered signal is then decimated by N. The decimation by N can be incorporated within the bandpass decimator such that the bandpass decimator operates at 1/N of the frequency of the ADC sampling clock. The signals from all bandpass decimators are summed together and the resultant IF samples are provided to two multipliers which downconvert the IF samples to I and Q baseband samples with an inphase and a quadrature sinusoid, respectively.

Abstract: A phase lock loop wherein the reference clock is divided by a variable divider which is capable of dividing the reference clock by a divider ratio of 2, 3, 4, . . . or M depending on the value of a control signal. The control signal is generated from a divider controller in response to a controller input. The noise shaping characteristics of the divider controller results in dithering of the variable divider ratios such that the average frequency of the divided reference clock is at the desired comparison frequency but the quantization noise from the fractional divide is pushed from low frequency to high frequency where it is more easily filtered. The noise shaper can be implemented with many bits of resolution to allow for a wide frequency control range and high frequency accuracy. A dither circuit to prevent limit cycling at the output of the noise shaper.