Patents by Inventor Leo M. Higgins, III

Leo M. Higgins, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8907485
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Patent number: 8853867
    Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sheila F. Chopin, Varughese Mathew, Leo M. Higgins, III, Chu-Chung Lee
  • Publication number: 20140287554
    Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: LEO M. HIGGINS, III
  • Publication number: 20140273352
    Abstract: A method includes forming a packaged integrated circuit that includes forming a lead frame by separating an outer portion of the metal structure into a plurality of leads by stamping. The plurality of leads have sides with a first concavity. The lead frame is further formed by performing an etch on the sides of the plurality of leads to achieve a second concavity on the sides of leads. The second concavity is greater than the first concavity. A semiconductor die is attached to a center portion of the metal structure. Electrical attachments are made between the die and the leads.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Leo M. Higgins, III, Sheila F. Chopin
  • Publication number: 20140225268
    Abstract: A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.
    Type: Application
    Filed: February 12, 2013
    Publication date: August 14, 2014
    Inventors: GEORGE R. LEAL, Leo M. Higgins, III, Tim V. Pham
  • Publication number: 20140213018
    Abstract: A method includes providing an integrated circuit (IC) die assembly that includes a substrate and an IC die mounted on a portion of a major surface of the substrate, dispensing an interface material on the IC die, positioning a portion of a heat spreader in contact with the interface material, and dispensing an adhesive between one side of the heat spreader facing the IC die assembly and exposed portions of a major surface of an encapsulant on the substrate.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Inventors: Leo M. Higgins III, Burton J. Carpenter
  • Patent number: 8754521
    Abstract: A packaged semiconductor device includes a package substrate, a semiconductor die on the package substrate, an encapsulant over the semiconductor die and package substrate, and a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion. The encapsulant includes an opening within a perimeter of the semiconductor die. The bottom surface of the pedestal portion of the heat spreader faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 17, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Burton J. Carpenter, Leo M. Higgins, III, Yuan Yuan
  • Publication number: 20140145339
    Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sheila F. CHOPIN, Varughese MATHEW, Leo M. HIGGINS, III, Chu-Chung LEE
  • Patent number: 8716066
    Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Leo M. Higgins, III
  • Publication number: 20140110801
    Abstract: A pressure sensor includes a first housing having a cavity. The pressure sensor further includes a pressure sensing device attached to a bottom of the cavity. The pressure sensor further includes a layer of gel over the pressure sensing device. The pressure sensor further includes a baffle in contact with the gel to reduce movement of the gel.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Inventor: LEO M. HIGGINS, III
  • Publication number: 20140077349
    Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced package (9) with exposed heat spreader lid array (96) designed to be optimized for compression mold encapsulation of an integrated circuit die (94) by including a perimeter reservoir regions (97r) in each heat spreader lid (96) for movement of mold compound (98) displaced during the mold compression process.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventor: Leo M. HIGGINS, III
  • Patent number: 8674509
    Abstract: A packaged semiconductor device comprises a package substrate comprising a first package substrate contact and a second package substrate contact, and a semiconductor die over the package substrate. The semiconductor device further includes electrical connections between signal contact pads of the die and the package substrate, and a heat spreader that comprises a first heat spreader portion which is electrically connected to a first signal contact pad and the first package substrate contact and provides an electrical conduction path and a thermal conduction path. A second heat spreader portion provides an electrical conduction path between a second signal contact pad and the second package substrate contact and a thermal conduction path between the die and package substrate. An insulating layer is positioned between the first and second heat spreader portions.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: March 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Burton J. Carpenter, Leo M. Higgins, III
  • Publication number: 20140054781
    Abstract: An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Inventors: Leo M. Higgins, III, Chu-Chung Lee
  • Publication number: 20140038356
    Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventor: Leo M. Higgins, III
  • Patent number: 8643197
    Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sheila F. Chopin, Varughese Mathew, Leo M. Higgins, III, Chu-Chung Lee
  • Publication number: 20130320548
    Abstract: A packaged semiconductor device comprises a package substrate comprising a first package substrate contact and a second package substrate contact, and a semiconductor die over the package substrate. The semiconductor device further includes electrical connections between signal contact pads of the die and the package substrate, and a heat spreader that comprises a first heat spreader portion which is electrically connected to a first signal contact pad and the first package substrate contact and provides an electrical conduction path and a thermal conduction path. A second heat spreader portion provides an electrical conduction path between a second signal contact pad and the second package substrate contact and a thermal conduction path between the die and package substrate. An insulating layer is positioned between the first and second heat spreader portions.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventors: BURTON J. CARPENTER, Leo M. Higgins, III
  • Publication number: 20130319129
    Abstract: A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Varughese Mathew, Sheila F. Chopin, Leo M. Higgins, III
  • Publication number: 20130221511
    Abstract: A method for forming a molded die assembly includes attaching a first major surface of a semiconductor die onto a package substrate; attaching a heat spreader to a second major surface of the semiconductor die, wherein the second major surface is opposite the first major surface, and wherein the semiconductor die, package substrate, and heat spreader form a die assembly; conforming a die release film to a transfer mold; closing the transfer mold around the die assembly such that the die release film is compressed against the heat spreader and a cavity is formed around the die assembly; transferring a thermoset material into the cavity; and releasing the die assembly from the die release film and the transfer mold.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 29, 2013
    Inventors: Leo M. Higgins, III, Burton J. Carpenter, Glenn G. Daves
  • Publication number: 20130181340
    Abstract: A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 18, 2013
    Inventors: Trent S. UEHLING, Lawrence S. KLINGBEIL, Mostafa VADIPOUR, Brett P. WILKERSON, Leo M. HIGGINS, III
  • Publication number: 20130037931
    Abstract: An apparatus and method of forming a semiconductor package includes having and applying, respectively, a thermal interface material on a semiconductor die. The semiconductor die is included on a die assembly. The semiconductor die is installed in a heat spreader. The heat spreader is at least partially filled with mold compound and the semiconductor die is at least partially immersed in the mold compound once the die assembly is mounted on the heat spreader. The mold compound is then cured.
    Type: Application
    Filed: August 8, 2011
    Publication date: February 14, 2013
    Inventor: LEO M. HIGGINS, III