Patents by Inventor Leonard E. Mess
Leonard E. Mess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8049342Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: July 27, 2009Date of Patent: November 1, 2011Assignee: Round Rock Research, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7999378Abstract: A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device.Type: GrantFiled: February 22, 2010Date of Patent: August 16, 2011Assignee: Round Rock Research, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7998792Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangements, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high-density low-profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: December 4, 2009Date of Patent: August 16, 2011Assignee: Round Rock Research, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7829991Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.Type: GrantFiled: October 18, 2007Date of Patent: November 9, 2010Assignee: Micron Technology, Inc.Inventors: Walter L. Moden, David J. Corisis, Leonard E. Mess, Larry D. Kinsman
-
Publication number: 20100148331Abstract: A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: ROUND ROCK RESEARCH, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7704794Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: November 13, 2006Date of Patent: April 27, 2010Assignee: Micron Technology, Inc.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Publication number: 20100078793Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangements, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high-density low-profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: ApplicationFiled: December 4, 2009Publication date: April 1, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Publication number: 20090286356Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: ApplicationFiled: July 27, 2009Publication date: November 19, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7408255Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.Type: GrantFiled: October 31, 2005Date of Patent: August 5, 2008Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
-
Patent number: 7400032Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.Type: GrantFiled: October 31, 2005Date of Patent: July 15, 2008Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
-
Patent number: 7396702Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.Type: GrantFiled: October 31, 2005Date of Patent: July 8, 2008Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
-
Patent number: 7375419Abstract: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The stacked multiple offset chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: September 1, 2004Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7285442Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.Type: GrantFiled: February 22, 2005Date of Patent: October 23, 2007Assignee: Micron Technology, Inc.Inventors: Walter L. Moden, David J. Corisis, Leonard E. Mess, Larry D. Kinsman
-
Patent number: 7279797Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.Type: GrantFiled: January 3, 2005Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
-
Patent number: 7262506Abstract: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: January 15, 2003Date of Patent: August 28, 2007Assignee: Micron Technology, Inc.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7229905Abstract: A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die paddle, and a semiconductor die mounted to the die paddle. The die paddle comprises a plurality of eyepoint features that extend from the die. The die comprises a first plurality of bonding pads and the lead fingers comprise a second plurality of bonding pads. The first and second bonding pads are interconnected by a plurality of connecting wires which are installed by the automated wire bonding system. The wire bonding system obtains an image of the lead frame and identifies the eyepoint features of the die paddle within the image so as to more accurately determine the positions of the second wire bonding pads of the lead frame with respect to the wire bonding system.Type: GrantFiled: February 16, 2005Date of Patent: June 12, 2007Assignee: Micron Technology, Inc.Inventors: Stuart L. Roberts, William J. Reeder, Leonard E. Mess
-
Patent number: 7166252Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture maybe constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.Type: GrantFiled: December 13, 2004Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventors: Derek J. Gochnour, Leonard E. Mess
-
Patent number: 6900528Abstract: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: June 21, 2001Date of Patent: May 31, 2005Assignee: Micron Technology, Inc.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 6869869Abstract: A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die paddle, and a semiconductor die mounted to the die paddle. The die paddle comprises a plurality of eyepoint features that extend from the die. The die comprises a first plurality of bonding pads and the lead fingers comprise a second plurality of bonding pads. The first and second bonding pads are interconnected by a plurality of connecting wires which are installed by the automated wire bonding system. The wire bonding system obtains an image of the lead frame and identifies the eyepoint features of the die paddle within the image so as to more accurately determine the positions of the second wire bonding pads of the lead frame with respect to the wire bonding system.Type: GrantFiled: May 16, 2003Date of Patent: March 22, 2005Assignee: Micron Technology, Inc.Inventors: Stuart L. Roberts, William J. Reeder, Leonard E. Mess
-
Patent number: 6864700Abstract: A system including an interposer and a coupler for electrically coupling a semiconductive device to an electrical apparatus. The system also includes (i) a substrate having of an electrically insulating, thermally conductive ceramic material; and (ii) an electrical conductor on the substrate having a receiving end for connecting to a semiconductive device and a terminal end for connecting to an electrical apparatus. The semiconductive device is electrically coupled to the electrical apparatus when the semiconductive device is connected to the receiving end of the electrical conductor and the terminal end of the electrical conductor is connected to the electrical apparatus. A thermally conductive coupler or connector connects the semiconductive device to the interposer. The thermally conductive interposer and connector conduct heat from the semiconductive device to the environment, thereby protecting the semiconductive device from overheating.Type: GrantFiled: February 9, 2000Date of Patent: March 8, 2005Assignee: Micron Technology, Inc.Inventor: Leonard E. Mess