Patents by Inventor Leonard E. Mess

Leonard E. Mess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6858926
    Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: February 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Walter L. Moden, David J. Corisis, Leonard E. Mess, Larry D. Kinsman
  • Patent number: 6838768
    Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: January 4, 2005
    Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
  • Patent number: 6830719
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 6815261
    Abstract: A molding machine for encapsulating electronic devices mounted on one side of a substrate, and having a ball-grid array, pin-grid array, or land-grid array on the opposite side, has a two member biased floating plate apparatus to compensate for variations in substrate thickness, and a gas collection/venting apparatus for relieving gases emitted from the non-encapsulated underside of the substrate.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: November 9, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Leonard E. Mess
  • Patent number: 6777965
    Abstract: An interposer for electrically coupling a semiconductive device to an electrical apparatus includes (i) a substrate comprised of an electrically insulating, thermally conductive ceramic material; and (ii) an electrical conductor on the substrate having a receiving end for connecting to a semiconductive device and a terminal end for connecting to an electrical apparatus. The semiconductive device is electrically coupled to the electrical apparatus when the semiconductive device is connected to the receiving end of the electrical conductor and the terminal end of the electrical conductor is connected to the electrical apparatus. A thermally conductive connector connects the semiconductive device to the interposer. The thermally conductive interposer and connector conduct heat from the semiconductive device to the environment, thereby protecting the semiconductive device from overheating.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: August 17, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Leonard E. Mess
  • Patent number: 6764549
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board. In the method, at least one printed circuit board is mounted to a clamping fixture support whereby a clamping fixture overlay is placed on top of the first printed circuit board.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: July 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 6760224
    Abstract: An apparatus for providing heat sinks or heat spreaders for stacked semiconductor devices. Alignment apparatus may be included for the alignment of the stacked semiconductor devices. An enclosure may be used as the heat sink or heat spreader.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: July 6, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Walter L. Moden, David J. Corisis, Larry D. Kinsman, Leonard E. Mess
  • Publication number: 20040104408
    Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.
    Type: Application
    Filed: November 12, 2003
    Publication date: June 3, 2004
    Inventors: Walter L. Moden, David J. Corisis, Leonard E. Mess, Larry D. Kinsman
  • Patent number: 6690188
    Abstract: A method testing a semiconductor device mounted upon an interposer. The interposer electrically couples the semiconductive device to an electrical apparatus and includes (i) a substrate comprised of an electrically insulating, thermally conductive ceramic material; and (ii) an electrical conductor on the substrate having a receiving end for connecting to the semiconductive device and a terminal end for connecting to the electrical apparatus. The semiconductive device is electrically coupled to the electrical apparatus when the semiconductive device is connected to the receiving end of the electrical conductor and the terminal end of the electrical conductor is connected to the electrical apparatus. A thermally conductive connector connects the semiconductive device to the interposer. The thermally conductive interposer and connector conduct heat from the semiconductive device to the environment, thereby protecting the semiconductive device from overheating.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Leonard E. Mess
  • Publication number: 20040011283
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 22, 2004
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 6650007
    Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: November 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Walter L. Moden, David J. Corisis, Leonard E. Mess, Larry D. Kinsman
  • Publication number: 20030205795
    Abstract: A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die paddle, and a semiconductor die mounted to the die paddle. The die paddle comprises a plurality of eyepoint features that extend from the die. The die comprises a first plurality of bonding pads and the lead fingers comprise a second plurality of bonding pads. The first and second bonding pads are interconnected by a plurality of connecting wires which are installed by the automated wire bonding system.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 6, 2003
    Inventors: Stuart L. Roberts, William J. Reeder, Leonard E. Mess
  • Publication number: 20030197271
    Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.
    Type: Application
    Filed: May 8, 2003
    Publication date: October 23, 2003
    Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
  • Publication number: 20030137042
    Abstract: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.
    Type: Application
    Filed: January 15, 2003
    Publication date: July 24, 2003
    Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
  • Patent number: 6592670
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board. In the method at least one printed circuit board is mounted to a clamping fixture support whereby a clamping fixture overlay is placed on top of the first printed circuit board.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: July 15, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Publication number: 20030128523
    Abstract: An apparatus for providing heat sinks or heat spreaders for stacked semiconductor devices. Alignment apparatus may be included for the alignment of the stacked semiconductor devices. An enclosure may be used as the heat sink or heat spreader.
    Type: Application
    Filed: February 25, 2003
    Publication date: July 10, 2003
    Inventors: Walter L. Moden, David J. Corisis, Larry D. Kinsman, Leonard E. Mess
  • Publication number: 20030111766
    Abstract: A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a clamping fixture assembly, which includes at least one clamping fixture support and at least one clamping fixture overlay. If desired, a plurality of printed circuit boards may be processed using an appropriate clamping fixture assembly. Furthermore, the clamping fixture may be constructed so a slight bow or curvature thereof can counter either a convex or concave bow or curvature of the printed circuit board.
    Type: Application
    Filed: February 5, 2003
    Publication date: June 19, 2003
    Inventors: Derek J. Gochnour, Leonard E. Mess
  • Patent number: 6577019
    Abstract: A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die paddle, and a semiconductor die mounted to the die paddle. The die paddle comprises a plurality of eyepoint features that extend from the die. The die comprises a first plurality of bonding pads and the lead fingers comprise a second plurality of bonding pads. The first and second bonding pads are interconnected by a plurality of connecting wires which are installed by the automated wire bonding system.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: June 10, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, William J. Reeder, Leonard E. Mess
  • Patent number: 6563217
    Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: May 13, 2003
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Walter L. Moden, Leonard E. Mess, Larry D. Kinsman
  • Patent number: 6558966
    Abstract: Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: May 6, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Leonard E. Mess, David J. Corisis, Walter L. Moden, Larry D. Kinsman