Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

Abstract: Integrated circuit structures having backside gate partial cut or backside trench contact partial cut and/or spit epitaxial structure are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first portion of a gate electrode is around the first stack of nanowires, a second portion of the gate electrode is around the second stack of nanowires, and a third portion of the gate electrode bridges the first and second portions of the gate electrode. A dielectric structure is between the first portion of the gate electrode and the second portion of the gate electrode, the dielectric structure over the third portion of the gate electrode. The dielectric structure is continuous along the first and second portions of the gate electrode and the first and second sub-fin structures.

Abstract: Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

Abstract: Integrated circuit structures having front-side-guided backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut are described. For example, an integrated circuit structure includes a first and second vertical stacks of horizontal nanowires or fins. A first gate structure is over the first vertical stack of horizontal nanowires or fin, and a second gate structure is over the second vertical stack of horizontal nanowires or fin, the second gate structure having voltage threshold (VT) different than a VT of the first gate structure. A conductive trench contact is adjacent to the first gate structure and the second gate structure. A dielectric sidewall spacer is between the first gate structure and the conductive trench contact, and between the second gate structure and the conductive trench contact. A dielectric cut plug structure is extending between the first gate structure and the second gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.

Abstract: Integrated circuit structures having backside contact extensions are described. In an example, a structure includes a first and second pluralities of horizontally stacked nanowires or fins. First and second gate stacks are over the first and second pluralities of horizontally stacked nanowires or fins. An epitaxial source or drain structure is between the first and second pluralities of horizontally stacked nanowires or fin. A dielectric structure is over the first gate stack, over the second gate stack, and over the epitaxial source or drain structure, the dielectric structure having an opening over the epitaxial source or drain. A conductive structure is in the opening in the dielectric structure and on the epitaxial source or drain structure, the conductive structure having a top surface below a top of the opening. A conductive extension is on the conductive structure, the conductive extension in and protruding above the opening in the dielectric structure.

Abstract: Integrated circuit structures having front-side-cut backside source or drain contacts are described. In an example, an integrated circuit structure includes a first gate stack over a first plurality of horizontally stacked nanowires or fin, and a second gate stack over a second plurality of horizontally stacked nanowires or fin. A first epitaxial source or drain structure is at an end of the first plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a backside contact structure thereon. A second epitaxial source or drain structure is at an end of the second plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is laterally between and in contact with the backside dielectric structure and the backside contact structure.

Abstract: Integrated circuit structures having a metal gate cut plug and an alignment structure are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate electrode is over the vertical stack of horizontal nanowires or the fin. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and past the conductive trench contact. A semiconductor structure is adjacent to a side of the dielectric cut plug structure opposite the gate electrode, the dielectric sidewall spacer, and the conductive trench contact. A dielectric structure covers a top and sides of the semiconductor structure, the dielectric structure in contact with the side of the dielectric cut plug structure.

Abstract: Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

Abstract: An IC device may include a support structure and a transistor built based on the support structure. The transistor may include an electrical contact over a semiconductor region in the transistor. The electrical contact may be a single structure formed by filling a single opening region with a conductive material. In an example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a deep via. The deep via may extend through the support structure and contact a backside metal layer for delivering power or signal to the semiconductor region. In another example, an end of the electrical contact may contact the semiconductor region, and another end of the electrical contact may contact a semiconductor region in another transistor. A dielectric structure may be between the two semiconductor regions.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut with source or drain depopulation, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut with source or drain depopulation, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin, a gate electrode, and a dielectric structure in a source or drain location at an end of the vertical stack of horizontal nanowires or the fin. A dielectric sidewall spacer is between the gate electrode and the dielectric structure, and first and second dielectric cut plug structures are extending through the gate electrode, through the dielectric sidewall spacer, and through the dielectric structure.

Abstract: An integrated circuit structure includes laterally adjacent first and second devices. The first device includes (i) a first source or drain region having a first plurality of portions, (ii) a first plurality of bodies, each body of the first plurality of bodies laterally extending from a corresponding one of the first plurality of portions, and (iii) a first source or drain contact including a first conductive material and coupled to the first plurality of portions. The second device includes (i) a second source or drain region having a second plurality of portions, (ii) a second plurality of bodies, each body of the second plurality of bodies laterally extending from a corresponding one of the second plurality of portions, and (iii) a second source or drain contact coupled to the second plurality of portions and including a second conductive material elementally different from the first conductive material.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut with channel depopulation, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut with channel depopulation, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact.

Abstract: Integrated circuit structures having varied epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a lateral width greater than the lateral width of the first epitaxial source or drain structure.

Abstract: Integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.

Abstract: Integrated circuit structures having varied etch-stop for epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width, and the first epitaxial source or drain structure beneath a first etch-stop layer.

Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.