Abstract: Integrated circuit structures having varied etch-stop for epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width, and the first epitaxial source or drain structure beneath a first etch-stop layer.

Abstract: Integrated circuit structures having varied epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a lateral width greater than the lateral width of the first epitaxial source or drain structure.

Abstract: Integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.

Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure is in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Abstract: Integrated circuit structures having fin cuts, and methods of fabricating integrated circuit structures having fin cuts, are described. For example, an integrated circuit structure includes a first fin structure or nanowire stack and sub-fin pairing separated from a second fin structure or nanowire stack and sub-fin pairing by a cut, wherein an end of the first fin structure or nanowire stack and sub-fin pairing is facing toward an end of the second fin structure or nanowire stack and sub-fin pairing. A first gate structure is overlying the first fin structure or nanowire stack and sub-fin pairing, and a second gate structure is overlying the second fin structure or nanowire stack and sub-fin pairing.

Abstract: Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.

Abstract: Integrated circuit structures having differentiated source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width and a composition. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having the composition of the first epitaxial source or drain structure, and the second epitaxial source or drain structure having a lateral width less than the lateral width of the first epitaxial source or drain structure.

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate structure is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure has a first portion laterally spaced apart from the epitaxial source or drain structure, a second portion vertically over the epitaxial source or drain structure, and a third portion between the first portion and the second portion. A dielectric plug is laterally between the epitaxial source or drain structure and the first portion of the conductive trench contact structure, wherein the third portion of the conductive trench contact structure is vertically over the dielectric plug.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

Abstract: Techniques to form semiconductor device conductive interconnections. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. Adjacent to the source or drain region, a deep via structure extends in a vertical direction through an entire thickness of the gate structure. The via structure includes a conductive via that is recessed below a top surface of the conductive contact. A conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

Abstract: Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a conductive via in a first dielectric layer. The integrated circuit structure also includes a conductive line in a second dielectric layer, the conductive including a conductive liner having a conductive barrier therein, the conductive barrier having a conductive fill therein, wherein the conductive liner is directly on the conductive via.

Abstract: A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

Abstract: Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.