Abstract: An integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin having a first lateral width. A first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. A second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width less than the first lateral width. A second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width, the fourth lateral width less than the second lateral width.

Abstract: Integrated circuit structures having internal spacer liners, and methods of fabricating integrated circuit structures having internal spacer liners, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An internal spacer liner is intervening between the internal gate spacer and the vertically adjacent ones of the stack of horizontal nanowires, and the internal spacer liner is intervening between the internal gate spacer and the gate structure.

Abstract: Techniques are provided herein to form semiconductor devices having cells that include forksheet devices with source or drain regions of the same dopant type on both sides of the forksheet dielectric spine. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The forksheet devices may include all p-type source or drain regions on both sides of the dielectric spine or all n-type source or drain regions on both sides of the dielectric spine. Using forksheet devices with the same dopant type allows for both forksheet transistors and gate-all-around (GAA) transistors to be included within the same cell. The cell boundaries may also be placed along the forksheet dielectric spines rather than along gate cuts, which provides greater flexibility when designing multi-height cells.

Abstract: Integrated circuit structures having deep via bar isolation are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes has a cut between first and second conductive structure portions. A cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for creating flyover trench connectors within a transistor structure, where a first portion of the trench connector is electrically coupled with a first epitaxial structure and where a second portion of the trench connector extends above but is not electrically coupled with a second epitaxial structure. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate plug includes a metal-containing dielectric material.

Abstract: Integrated circuit structures having partial channel cap removal, and methods of fabricating integrated circuit structures having partial channel cap removal, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires. A dielectric channel cap has an opening over the stack of nanowires. A gate electrode is over and around the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires. A conductive tap is on the gate electrode and in the opening in the dielectric channel cap. A dielectric layer is on the gate electrode and laterally adjacent to the conductive tap.

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

Abstract: Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Abstract: Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

Abstract: Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

Abstract: Techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. In an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. A backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.

Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.

Abstract: Techniques to form semiconductor devices having one or more epitaxial source or drain regions formed between dielectric walls that separate each adjacent pair of source or drain regions. In an example, a semiconductor device includes a semiconductor region extending in a first direction from a source or drain region. Dielectric walls extend in the first direction adjacent to opposite sides of the source or drain region. The first and second dielectric walls also extend in the first direction through a gate structure present over the semiconductor region. A dielectric liner exists between at least a portion of the first side of the source or drain region and the first dielectric wall and/or at least a portion of the second side of the source or drain region and the second dielectric wall. The dielectric walls may separate the source or drain region from other adjacent source or drain regions.

Abstract: Techniques are provided herein to form semiconductor devices arranged between a gate cut on one side and a deep backside via on the other side. A row of semiconductor devices each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Each semiconductor device may be separated from an adjacent semiconductor device along the second direction by either a gate cut or a deep backside via. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure and the deep backside via may include a conductive layer and a dielectric barrier that also extend through at least an entire thickness of the gate structure. Each semiconductor device may include a gate cut on one side and a deep backside via on the other side.

Abstract: Techniques to form an integrated circuit having a bridging contact structure. A bridging contact structure may, for example, bridge between source/drain contacts and to an adjacent gate electrode within the same device layer. In an example, a gate cut structure extends in a first direction to separate the source or drain regions and gate structures of neighboring semiconductor devices. Contacts may be formed over the source or drain regions of the neighboring devices on opposite sides of the gate cut along a second direction orthogonal to the first direction. A portion of the gate cut is replaced with a first conductive bridge between the source or drain contacts. A portion of one or more dielectric barriers between one of the source or drain contacts and an adjacent gate electrode is replaced with a second conductive bridge in the first direction between the source or drain contact and the gate structure.

Abstract: Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. In an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. The contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.

Abstract: Techniques are provided herein to form semiconductor devices having one or more source or drain regions with backside contacts that are separated using dielectric walls. In an example, a first semiconductor device includes a first semiconductor region, such as one or more first nanoribbons, extending from a first source or drain region, and a second semiconductor device including a second semiconductor region, such as one or more second nanoribbons, extending from a second source or drain region adjacent to the first source or drain region. A first conductive contact abuts the underside of the first source or drain region and a second conductive contact abuts the underside of the second source or drain region. A dielectric wall extends between the first and second contacts, thus separating them from contacting each other. The dielectric wall also extends between the first source or drain region and the second source or drain region.