Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure is in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.

Abstract: An impact attenuation system comprises an aluminum honeycomb sheet having a top surface and a bottom surface. The aluminum honeycomb sheet defines a plurality of approximately hexagonally shaped cells. The bottom surface defines a single sheet of contiguous cells and the top surface defines two or more islands of contiguous cells separated by one or more slits. At least a portion of one or both of the top surface and bottom surface may be covered by a polymer skin. The polymer skin may comprise carbon fibers and/or fiberglass.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Abstract: Methods and architectures for forming metal line plugs that define separations between two metal line ends, and for forming vias that interconnect the metal lines to an underlying contact. The line plugs are present in-plane with the metal lines while vias connecting the lines are in an underlying plane. One lithographic plate or reticle that prints lines at a given pitch (P) may be employed multiple times, for example each time with a pitch halving (P/2), or pitch quartering (P/4) patterning technique, to define both metal line ends and metal line vias. A one-dimensional (1D) grating mask may be employed in conjunction with cross-grating (orthogonal) masking structures that are likewise amenable to pitch splitting techniques.

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

Abstract: An impact attenuation system comprises an aluminum honeycomb sheet having a top surface and a bottom surface. The aluminum honeycomb sheet defines a plurality of approximately hexagonally shaped cells. The bottom surface defines a single sheet of contiguous cells and the top surface defines two or more islands of contiguous cells separated by one or more slits. At least a portion of one or both of the top surface and bottom surface may be covered by a polymer skin. The polymer skin may comprise carbon fibers and/or fiberglass.

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.

Abstract: Gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, and method of fabricating gate-all-around integrated circuit structures having low aspect ratio isolation structures and subfins, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first subfin. A second vertical arrangement of horizontal nanowires is above a second subfin laterally adjacent the first subfin. An isolation structure is laterally between the first subfin and the second subfin, the isolation structure having a maximum height and a maximum width with a maximum height to maximum width ratio of less than 3:1.

Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

Abstract: The digital 3D/360° camera system is an omnidirectional stereoscopic device for capturing image data that may be used to create a 3-dimensional model for presenting a 3D image, a 3D movie, or 3D animation. The device uses multiple digital cameras, arranged with overlapping fields of view, to capture image data covering an entire 360° scene. The data collected by one, or several, digital 3D/360° camera systems can be used to create a 3D model of a 360° scene by using triangulation of the image data within the overlapping fields of view.

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.