Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Abstract: An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.

Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.

Abstract: An embodiment includes an apparatus comprising: first and second semiconductor fins that are parallel to each other; a first gate, on the first fin, including a first gate portion between the first and second fins; a second gate, on the second fin, including a second gate portion between the first and second fins; a first oxide layer extending along a first face of the first gate portion, a second oxide layer extending along a second face of the second gate portion, and a third oxide layer connecting the first and second oxide layers to each other; and an insulation material between the first and second gate portions; wherein the first, second, and third oxide layers each include an oxide material and the insulation material does not include the oxide material. Other embodiments are described herein.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Abstract: The digital 3D/360° camera system is an omnidirectional stereoscopic device for capturing image data that may be used to create a 3-dimensional model for presenting a 3D image, a 3D movie, or 3D animation. The device uses multiple digital cameras, arranged with overlapping fields of view, to capture image data covering an entire 360° scene. The data collected by one, or several, digital 3D/360° camera systems can be used to create a 3D model of a 360° scene by using triangulation of the image data within the overlapping fields of view.

Abstract: A cartridge mounting an air treatment material has a housing. The air treatment material is received within the housing, and spaced from inner walls of the housing by a plurality of resilient sheets. The air treatment material is hydroxide sheets. There is an inlet direction into the housing for air flowing across the air treatment material and an outlet opening on an opposed end of the housing. There are top and bottom surfaces and side surfaces forming a perimeter about the air treatment material. The resilient sheets extend substantially continuously across the side surfaces and the top and bottom surfaces at least at the inlet end to increase airflow across the air treatment material. An enclosed inhabited space is also disclosed and claimed.

Abstract: Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.

Abstract: Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

Abstract: The digital 3D/360° camera system is an omnidirectional stereoscopic device for capturing image data that may be used to create a 3-dimensional model for presenting a 3D image, a 3D movie, or 3D animation. The device uses multiple digital cameras, arranged with overlapping fields of view, to capture image data covering an entire 360° scene. The data collected by one, or several, digital 3D/360° camera systems can be used to create a 3D model of a 360° scene by using triangulation of the image data within the overlapping fields of view.

Abstract: Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a method includes forming a first plurality of conductive lines in a first sacrificial material formed above a substrate. The first plurality of conductive lines is formed along a direction of a BEOL metallization layer and is spaced apart by a pitch. The method also includes removing the first sacrificial material, forming a second sacrificial material adjacent to sidewalls of the first plurality of conductive lines, and then forming a second plurality of conductive lines adjacent the second sacrificial material. The second plurality of conductive lines is formed along the direction of the BEOL metallization layer, is spaced apart by the pitch, and is alternating with the first plurality of conductive lines. The method also includes removing the second sacrificial layer.

Abstract: A self locating tie bar guide for use with a tie bar. The tie bar guide defines a passage into which the tie bar is received. A tie bar receiving portion is shiftable between an open orientation in which the tie bar can be inserted into the passage and a closed orientation in which the tie bar is held in the passage. A resilient engaging member that engages a prelocated opening in the tie bar is resiliently biased toward the tie bar when the receiving portion is in the open orientation. The resilient tie bar engaging member is shiftable away from the tie bar when the receiving portion is in the closed orientation by contact between a portion of the resilient engaging member and another portion of the tie bar guide.

Abstract: Methods and architectures for self-aligned build-up of patterned features. An initial patterned feature aspect ratio may be maintained or increased, for example to mitigate erosion of the feature during one or more subtractive device fabrication processes. A patterned feature height may be increased without altering an effective spacing between adjacent features that may be further relied upon, for example to further pattern an underlying material. A patterned feature may be conformally capped with a material, such as a metal or dielectric, in a self-aligned manner, for example to form a functional device layer on an initial pattern having a suitable space width-to-line height aspect ratio without the use of a masked etch to define the cap.

Abstract: The present specification is directed to systems, devices, and methods of portable enteral pump systems for feeding and/or flushing an ambulatory patient. Embodiments provide an enteral pumping device that may be loaded by a patient from a front and a top side of the pumping device and is therefore more convenient to use. Further, embodiments incorporate a single rotor pump for dual-use purposes of feeding nutrients and flushing fluids to the patient. A pinch valve is placed between the parallel sides of the two tubes to cut off fluid flow when required. At least one sensor is also placed between the rotor pump and an outlet. The sensors are used to detect occlusions and the type of disposables used, among other purposes.

Abstract: Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate, the dielectric lines raised above the metal lines. A hardmask layer is formed on the metal lines of the lower metallization layer, between and co-planar with the dielectric lines of the lower metallization layer. A grating structure is formed above and orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. A mask is formed above the grating structure. Select regions of the hardmask layer are removed to expose select regions of the metal lines of the lower metallization layer. Metal vias are formed on the select regions of the metal lines of the lower metallization layer.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

Abstract: A visor system for a helmet includes a lens sized to extend across at least a portion of a user's face, a frame secured along a top portion of the lens and configured to receive and abut against a front surface of the helmet, a first fastener coupled to a first end of the frame by a first flexible attachment, and a second fastener coupled to a second end of the frame by a second flexible attachment. The visor system may further include a first anchor releasably securable to the first fastener, the first anchor being mountable onto a first portion of the helmet, and a second anchor releasably securable to the second fastener, the second anchor being mountable onto a second portion of the helmet.

Abstract: An apparatus, system, and/or method that integrates excitable light emitting materials (that are transparent) into any surface to display an image. Light emitting materials may be integrated into uneven, irregular and/or random surfaces, displays may be formed on objects that are not practical for flat panel displays (e.g. steering wheels). Light emitting materials may be integrated onto or into the surface of a flat panel display that is responsive to excitation light of a laser pointer, thus allowing flat panel displays to be more effectively used in presentation applications. Since the light emitting materials are transparent, application of light emitting materials into objects does not obstruct the view of the objects when the light emitting materials are not being used to display images.