Abstract: A structure and process for packaging RF MEMS and other devices employs a substrate of silicon, for example, and a cap of glass, for example, having cavities to receive the devices. MEMS or other devices are supported on an upper surface of the substrate, into which metal-filled blind vias are formed. The cap is attached to the substrate, so as to enclose designated MEMS or other devices in the cavities. The substrate is then thinned so as to expose the metal of the vias at a lower surface of the substrate. Electrical connecting elements such as solder balls are then applied to the metal of the vias. The resultant composite substrate is then divided to provide individual packaged devices.

Abstract: A thin-film RC circuit element suitable for a transmission line termination circuit is prepared by a process wherein 1) a first metal layer of an anodizable metal is deposited on a substrate; 2) the exposed surface of the anodizable metal layer is anodized to produce an oxide layer, 3) a second metal layer of electrically conductive metal is provided on the oxide layer, and 4) the first metal layer is etched to form an electrically resistive conductive path electrically connected to the region f the first metal layer beneath the second metal layer. A thin-film RC circuit element is also provided having a first layer of an anodizable metal formed on an electrically insulating substrate so as to provide two capacitor plates connected by a resistive strip, an oxide layer formed on the capacitor plates, and upper capacitor plates positioned on the oxide layer in register with the lower capacitor plates.

Abstract: A capacitive structure is made with thin film capacitor plates substantially surrounding an opening cavity for accommodating a chip. The capacitive structure includes at least one capacitor and is mounted around the periphery of a ball grid array (BGA) having a flip chip in the opening. The capacitive structure provides a high capacitance with a low parasitic inductance.

Abstract: An interconnected mesh plane system includes at least a pair of adjacent metal layers separated by dielectric, each layer having a plurality of spaced power, ground, and signal conductors extending in the same direction, with the conductors of one layer of the pair transverse to the conductors of the other layer, and with conductors of one layer connected to corresponding conductors of the other layer. The width of at least one signal conductor is increased to reduce signal loss, and the width of spaces between such a signal conductor and adjacent power and/or ground conductors is increased to provide a predetermined desired characteristic impedance of a transmission line that includes such a signal conductor.

Abstract: Surface applied passive devices for use on electronic circuit boards are formed by applying layers of conductive, insulating, and other material to a thin polymer film carrier. The surface applied passives are thin enough to fit underneath standard integrated circuit packages in order to conserve space on the circuit board. Resistors, capacitors, inductors and other passive circuits may be formed on thin polymer films, less than 8 mils thick. This significantly aids in conserving space on an electronic circuit board.

Abstract: A method of forming a capacitor comprises: providing a first metallic thin-film layer; forming a dielectric thin-film layer of an anodized metal on a side of said first metallic layer; providing a second metallic thin-film layer on a side of the dielectric layer opposite the first metallic layer; and excising an area of the resulting structure to obtain at least one capacitor having a pair of electrode plate structures constituted by portions of said first and second metallic layers separated by a portion of said dielectric layer, and having connection points at adjacent electrode plate edges which are accessible from a same side of the capacitor and effective for operatively connecting the capacitor such that the capacitor does not exhibit an inductive resonance below a frequency of at least 1 GHz.

Abstract: An interconnected mesh plane system includes at least a pair of adjacent metal layers separated by dielectric, each layer having a plurality of spaced power, ground, and signal conductors extending in the same direction, with the conductors of one layer of the pair transverse to the conductors of the other layer, and with conductors of one layer connected to corresponding conductors of the other layer. The width of at least one signal conductor is increased to reduce signal loss, and the width of spaces between such a signal conductor and adjacent power and/or ground conductors is increased to provide a predetermined desired characteristic impedance of a transmission line that includes such a signal conductor.

Abstract: A thin-film RC circuit element (100) suitable for a transmission line termination circuit is prepared by a process wherein 1) a first metal layer (104) of an anodizable metal is deposited on a substrate (102); 2) the exposed surface of the anodizable metal layer is anodized to produce an oxide layer (106); 3) a second metal layer (108) of electrically conductive metal is provided on the oxide layer, and 4) the first metal layer is etched to form an electrically resistive conductive path (112) electrically connected to the region of the first metal layer beneath the second metal layer. A thin-film RC circuit element is also provided having a first layer of an anodizable metal (104) formed on an electrically insulating substrate (102) so as to provide two capacitor plates (104) connected by a resistive strip (112), an oxide layer (106) formed on the capacitor plates, and upper capacitor plates (108) positioned on the oxide layer in register with the lower capacitor plates.

Abstract: A capacitor having a floating plate-shaped electrode, at least two patterned plate electrodes overlying the floating plate-shaped electrode, and a dielectric layer therebetween. The resulting structure exhibits high two-port insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than −40 dB over a range from 1 GHz to 10 GHz.

Abstract: A capacitive structure is made with thin film capacitor plates substantially surrounding an opening cavity for accommodating a chip. The capacitive structure includes at least one capacitor and is mounted around the periphery of a ball grid array (BGA) having a flip chip in the opening . The capacitive structure provides a high capacitance with a low parasitic inductance.

Abstract: Surface applied passive devices for use on electronic circuit boards are formed by applying layers of conductive, insulating, and other material to a thin polymer film carrier. The surface applied passives are thin enough to fit underneath standard integrated circuit packages in order to conserve space on the circuit board. Resistors, capacitors, inductors and other passive circuits may be formed on thin polymer films, less than 8 mils thick. This significantly aids in conserving space on an electronic circuit board.

Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.

Abstract: A capacitor having a floating plate-shaped electrode, at least two patterned plate electrodes overlying the floating plate-shaped electrode, and a dielectric layer therebetween. The resulting structure exhibits high two-part insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than −40 dB over a range from 1 GHz to 10 GHz.

Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.

Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.

Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.

Abstract: A capacitor exhibits high two-port insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than −40 dB over a range from 1 GHz to 10 GHz and no inductive resonance below a frequency of at least 1 GHz.

Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.

Abstract: A capacitor having a floating plate-shaped electrode, at least two patterned plate electrodes overlying the floating plate-shaped electrode, and a dielectric layer therebetween. The resulting structure exhibits high two-port insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than -40 dB over a range from 1 GHz to 10 GHz.

Abstract: Disclosed is an electroplating method and products made therefrom, which in one embodiment includes using a current density J.sub.O, to form a conductive metal layer having a surface roughness no greater than the surface roughness of the underlying member. In another embodiment of electroplating a substrate surface having peaks and valleys, the method includes electroplating a conductive metal onto the peaks to cover the peaks with the conductive metal, and into the valleys to substantially fill the valleys with the conductive metal.