Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

Abstract: A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract: An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a functional region, doped with a second conductivity type, arranged in an active area of the structural layer at the top surface, in the proximity of an edge area of the integrated device, which externally surrounds the active area; and an edge termination region, doped with the second conductivity type, joined to the functional region and arranged in the edge area. The edge termination region has a doping profile and a junction depth that vary in a first direction parallel to the plane.

Abstract: A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate is provided in a trench extending into the epitaxial region from the front surface. An emitter includes a body extending into the epitaxial region at a first side of the trench and a source extending into the body region from the front surface at the trench. A dummy emitter extends into the epitaxial region from the front surface at a second side of the trench opposite said first side. The dummy emitter lacks the source. The gate extends along a first wall of the trench facing the emitter region. A dummy gate is formed in the trench in a manner electrically isolated from the gate and extending along a second wall of the trench opposite said first wall.

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

Abstract: A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate is provided in a trench extending into the epitaxial region from the front surface. An emitter includes a body extending into the epitaxial region at a first side of the trench and a source extending into the body region from the front surface at the trench. A dummy emitter extends into the epitaxial region from the front surface at a second side of the trench opposite said first side. The dummy emitter lacks the source. The gate extends along a first wall of the trench facing the emitter region. A dummy gate is formed in the trench in a manner electrically isolated from the gate and extending along a second wall of the trench opposite said first wall.

Abstract: A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate is provided in a trench extending into the epitaxial region from the front surface. An emitter includes a body extending into the epitaxial region at a first side of the trench and a source extending into the body region from the front surface at the trench. A dummy emitter extends into the epitaxial region from the front surface at a second side of the trench opposite said first side. The dummy emitter lacks the source. The gate extends along a first wall of the trench facing the emitter region. A dummy gate is formed in the trench in a manner electrically isolated from the gate and extending along a second wall of the trench opposite said first wall.

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

Abstract: A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate is provided in a trench extending into the epitaxial region from the front surface. An emitter includes a body extending into the epitaxial region at a first side of the trench and a source extending into the body region from the front surface at the trench. A dummy emitter extends into the epitaxial region from the front surface at a second side of the trench opposite said first side. The dummy emitter lacks the source. The gate extends along a first wall of the trench facing the emitter region. A dummy gate is formed in the trench in a manner electrically isolated from the gate and extending along a second wall of the trench opposite said first wall.

Abstract: A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract: An embodiment of a method for manufacturing a power device with conductive gate structures inside etched trenches. Such trenches include sidewalls and a bottom, wherein covering the sidewalls and the bottom of the trench is a first insulating coating layer. In the formation of the conductive gate structure, openings within the first material in the trench are made such that a conductive central region of a second conductive material having a different resistivity than the first conductive material are able to be electrically coupled together through a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract: An electronic power device for controlling a load includes: a high-voltage integrated switch having an output terminal to be connected to the load; an integrated, and low-voltage driving circuit for driving the switch, and a start-up integrated circuit comprising a high-voltage resistor and such that it can be enabled, during a step of turning on the power device, in order to activate the driving circuit. The switch and the start-up circuit are integrated in a first semiconductor chip and the driving circuit is integrated in a different, second semiconductor chip.

Abstract: An electronic power device for controlling a load includes: a high-voltage integrated switch having an output terminal to be connected to the load; an integrated, and low-voltage driving circuit for driving the switch, and a start-up integrated circuit comprising a high-voltage resistor and such that it can be enabled, during a step of turning on the power device, in order to activate the driving circuit. The switch and the start-up circuit are integrated in a first semiconductor chip and the driving circuit is integrated in a different, second semiconductor chip.

Abstract: A semiconductor power device includes an insulated gate and a trench-gate structure. The trench-gate structure is formed on a semiconductor substrate covered by an epitaxial layer. The trench is formed in the semiconductor to form the device gate region. A dielectric coating is provided on the inner and bottom walls of the trench. The gate region includes a conductive spacer layer on the coating layer only on the inner walls of the trench.

Abstract: A junction device including at least a first type semiconductor region and a second type semiconductor region a, which are arranged contiguous to one another and have a first and, respectively, a second type of conductivity, which are opposite to one another, and a first and a second biasing region (; the device is moreover provided with a resistive region, which has the first type of conductivity and extends from the first type semiconductor region and is contiguous to the second type semiconductor region so as to form a resistive path between the first and the second biasing regions.

Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.