Patents by Inventor Leonardo Fragapane

Leonardo Fragapane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140138739
    Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Angelo MAGRI', Antonino Sebastiano ALESSANDRIA, Stefania FORTUNA, Leonardo FRAGAPANE
  • Patent number: 8664713
    Abstract: A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: March 4, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Angelo Magri, Antonino Sebastiano Alessandria, Stefania Fortuna, Leonardo Fragapane
  • Patent number: 8637369
    Abstract: An embodiment of a method for manufacturing a power device with conductive gate structures inside etched trenches. Such trenches include sidewalls and a bottom, wherein covering the sidewalls and the bottom of the trench is a first insulating coating layer. In the formation of the conductive gate structure, openings within the first material in the trench are made such that a conductive central region of a second conductive material having a different resistivity than the first conductive material are able to be electrically coupled together through a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 28, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Angelo Magri, Antonino Sebastiano Alessandria, Stefania Fortuna, Leonardo Fragapane
  • Publication number: 20120220090
    Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
    Type: Application
    Filed: March 1, 2012
    Publication date: August 30, 2012
    Applicant: STMICROELECTRONICS S.r.I.
    Inventors: Angelo MAGRI, Antonino Sebastiano ALESSANDRIA, Stefania FORTUNA, Leonardo FRAGAPANE
  • Patent number: 7782637
    Abstract: An electronic power device for controlling a load includes: a high-voltage integrated switch having an output terminal to be connected to the load; an integrated, and low-voltage driving circuit for driving the switch, and a start-up integrated circuit comprising a high-voltage resistor and such that it can be enabled, during a step of turning on the power device, in order to activate the driving circuit. The switch and the start-up circuit are integrated in a first semiconductor chip and the driving circuit is integrated in a different, second semiconductor chip.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: August 24, 2010
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorenzo Maurizio Selgi, Leonardo Fragapane, Luigi Arcuri
  • Publication number: 20100163978
    Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.
    Type: Application
    Filed: December 22, 2009
    Publication date: July 1, 2010
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Angelo MAGRI, Antonino Sebastiano ALESSANDRIA, Stefania FORTUNA, Leonardo FRAGAPANE
  • Publication number: 20080002446
    Abstract: An electronic power device for controlling a load includes: a high-voltage integrated switch having an output terminal to be connected to the load; an integrated, and low-voltage driving circuit for driving the switch, and a start-up integrated circuit comprising a high-voltage resistor and such that it can be enabled, during a step of turning on the power device, in order to activate the driving circuit. The switch and the start-up circuit are integrated in a first semiconductor chip and the driving circuit is integrated in a different, second semiconductor chip.
    Type: Application
    Filed: June 5, 2007
    Publication date: January 3, 2008
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Lorenzo Selgi, Leonardo Fragapane, Luigi Arcuri
  • Patent number: 7205607
    Abstract: A semiconductor power device includes an insulated gate and a trench-gate structure. The trench-gate structure is formed on a semiconductor substrate covered by an epitaxial layer. The trench is formed in the semiconductor to form the device gate region. A dielectric coating is provided on the inner and bottom walls of the trench. The gate region includes a conductive spacer layer on the coating layer only on the inner walls of the trench.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: April 17, 2007
    Assignee: STMicroelectronics S.R.L
    Inventors: Antonino Sebastiano Alessandria, Leonardo Fragapane, Angelo Magri
  • Patent number: 7091559
    Abstract: A junction device including at least a first type semiconductor region and a second type semiconductor region a, which are arranged contiguous to one another and have a first and, respectively, a second type of conductivity, which are opposite to one another, and a first and a second biasing region (; the device is moreover provided with a resistive region, which has the first type of conductivity and extends from the first type semiconductor region and is contiguous to the second type semiconductor region so as to form a resistive path between the first and the second biasing regions.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: August 15, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Leonardo Fragapane, Antonino Alessandria
  • Publication number: 20050145977
    Abstract: A semiconductor power device includes an insulated gate and a trench-gate structure. The trench-gate structure is formed on a semiconductor substrate covered by an epitaxial layer. The trench is formed in the semiconductor to form the device gate region. A dielectric coating is provided on the inner and bottom walls of the trench. The gate region includes a conductive spacer layer on the coating layer only on the inner walls of the trench.
    Type: Application
    Filed: November 19, 2004
    Publication date: July 7, 2005
    Inventors: Antonino Alessandria, Leonardo Fragapane, Angelo Magri
  • Publication number: 20050139913
    Abstract: A method for manufacturing a semiconductor power device with an insulated gate and trench-gate structure integrated on a semiconductor substrate includes providing a body region in the semiconductor substrate, forming a surface source region on the body region, etching the semiconductor substrate and forming a trench to form the trench-gate structure. The method also includes forming a deep portion of the source region along the trench.
    Type: Application
    Filed: November 23, 2004
    Publication date: June 30, 2005
    Inventors: Antonino Alessandria, Leonardo Fragapane
  • Publication number: 20040262684
    Abstract: A junction device including at least a first type semiconductor region and a second type semiconductor region a, which are arranged contiguous to one another and have a first and, respectively, a second type of conductivity, which are opposite to one another, and a first and a second biasing region (; the device is moreover provided with a resistive region, which has the first type of conductivity and extends from the first type semiconductor region and is contiguous to the second type semiconductor region so as to form a resistive path between the first and the second biasing regions.
    Type: Application
    Filed: April 1, 2004
    Publication date: December 30, 2004
    Inventors: Leonardo Fragapane, Antonino Alessandria
  • Patent number: 6787881
    Abstract: An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: September 7, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Romeo Letor, Antonino Torres, Leonardo Fragapane
  • Publication number: 20030006829
    Abstract: A power device with integrated voltage stabilizing circuit, comprising a MOS transistor that is connected in parallel to a circuit that is integrated in a power device, at least one Zener diode with a series-connected resistor being connected in parallel to the transistor, the gate terminal of the transistor being connected to an intermediate node between the Zener diode and the resistor, the anode terminal of the Zener diode and the drain terminal of the transistor being connected to an input voltage of the circuit.
    Type: Application
    Filed: July 5, 2002
    Publication date: January 9, 2003
    Applicant: STMicroelectronics S.R.L.
    Inventors: Antonino Alessandria, Leonardo Fragapane
  • Publication number: 20020117732
    Abstract: An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.
    Type: Application
    Filed: January 4, 2002
    Publication date: August 29, 2002
    Applicant: STMicroelectronics S.r.l.
    Inventors: Romeo Letor, Antonino Torres, Leonardo Fragapane
  • Publication number: 20020113247
    Abstract: A method of manufacturing an electronic structure, which structure comprises a first power device and a second unidirectional device, both integrated in the same protective package. The first device having at least first and second electrodes of the first device, with said first electrode of the first device being attached to the package. The second device having first and second electrodes of the second device, wherein the first electrode of the second device is superposed on the second electrode of the first device and connected electrically to the second electrode of the first device.
    Type: Application
    Filed: February 8, 2002
    Publication date: August 22, 2002
    Applicant: STMicroelectronics S.r.I.
    Inventors: Angelo Magri, Leonardo Fragapane
  • Patent number: 6271061
    Abstract: A semiconductor power device comprising an insulated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer. Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: August 7, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ferruccio Frisina, Leonardo Fragapane
  • Patent number: 6222248
    Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: April 24, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Leonardo Fragapane
  • Patent number: 6169300
    Abstract: An Insulated Gate Bipolar Transistor includes a semiconductor substrate of a first conductivity type forming a first electrode of the device, a semiconductor layer of a second conductivity type superimposed over said substrate, a plurality of body regions of the first conductivity type formed in the semiconductor layer, a first doped region of the second conductivity type formed inside each body region, an insulated gate layer superimposed over portions of the semiconductor layer between the body regions and forming a control electrode of the device, a conductive layer insulatively disposed over the insulated gate layer and contacting each body region and each doped region formed therein, the conductive layer forming a second electrode of the device.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: January 2, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Leonardo Fragapane
  • Patent number: RE40222
    Abstract: A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first region, a first electrode in contact with the first termination region, and a second electrode shaped in the form of a frame close to the edge of the chip and connected to a third electrode in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode is in contact with the first region. The termination structure also comprises a fifth electrode in contact with the epitaxial layer along a path parallel to the edge of the first termination region and connected to the second electrode and a second P type termination region that surrounds the fifth electrode and a sixth electrode, and which is in contact with the second termination region, connected to the first electrode.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: April 8, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventor: Leonardo Fragapane