Abstract: An automatic method of diagnosing pathologies of distal parts of limbs of a quadruped is based on the processing (101-109) of thermographic images of such limbs. The processing includes the following steps: identifying (103, 104), in each thermographic image and for each limb concerned by the diagnosis, an area containing the distal part, and extracting an identified image of the distal part from said area; validating (104) identified images complying with predetermined criteria as images utilisable for diagnostic purposes; extracting (105) features that are significant for the detection of the presence and kind of pathology from the validated images; and classifying (106) the distal part of a limb as unaffected by pathologies or as affected by a specific pathology on the basis of such features. There are also provided an apparatus and information technology product containing program codes for implementing the method when loaded into a processing device.

Abstract: The present invention relates to a signal processor, and more particularly, to systems, devices and methods of using a comprehensive sensor fusion algorithm to integrate sensor data collected by accelerometers, gyroscopes and magnetometers. The signal processor dynamically applies a Complementary Filter to merge a rotation based gyro output and a FQA output that is obtained by combining acceleration rates and magnetic field magnitudes. Therefore, motion information is derived to generate a motion control signal. Such a comprehensive sensor fusion algorithm significantly reduces the complexity of computation, and the power and area overhead is controlled. As a result, the signal processor may be implemented based on local computation capability of a sensor system, and its integration within such a sensor system is made possible without relying on an external microprocessor.

Abstract: A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module.

Abstract: Various embodiments of the invention provide for fully-integrated, low-latency power reduction in multi-sensor systems. In certain embodiments, power consumption is minimized by modulating power and mode of operation of gyroscopes, magnetometers, and accelerometers under certain conditions. Certain embodiments provide for reduction of power consumption by the use of emulated gyroscope data.

Abstract: A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module.

Abstract: A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module.

Abstract: A communication interface hub includes multiple ports, where one of the ports is an upstream port operative to be in direct and/or indirect communication with a host and at least one other of the ports is a downstream port operative to be in direct and/or indirect communication with at least one device. At least one hub core is coupled to the ports and implements at least one physical hub, and at least one virtual hub core is coupled to the ports and implements at least one virtual hub. The virtual hub is detectable as at least one physical hub by the host to cause the host to allocate an additional time delay in waiting for responses to signals output by the host.

Abstract: In an embodiment, an analog front end (AFE) bridge for a SLPI PHY includes: an AFE LINK-side circuit having at least one pair of differential LINK-side nodes which does not conform to SLPI PHY specifications; an AFE PHY-side circuit having a pair of differential PHY-side nodes conforming to SLPI PHY specifications, wherein the AFE PHY-side circuit is coupled to the AFE LINK-side circuit; and a termination control circuit coupled to the AFE PHY-side circuit. A method of bridging a legacy LINK circuit to a SLPI PHY circuit includes: communicating with a legacy LINK circuit with a legacy LINK protocol; communicating with a SLPI PHY circuit with a SLPY PHY protocol over a differential pair; converting outputs of the legacy LINK circuit into inputs of the SLPI PHY circuit; converting outputs of the SLPI PHY circuit into inputs of the legacy LINK circuit; controlling a termination of the differential pair.

Abstract: A cable detection circuit for a device, set forth by way of example and not limitation, includes a generator circuit operative to provide currents on a line of a communication interface. A controller is coupled to the generator circuit and operative to detect an amount of capacitance on the line based on the provided currents. The controller is operative provide an output based on the detected amount of capacitance, the output indicating whether a cable is connected to the device via the communication interface.

Abstract: A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module.

Abstract: Communication interfaces having reduced signal lines. In one aspect, a physical layer circuit, set forth by way of example and not limitation, interfaces a link controller and a device communication bus, and includes a wrapper coupled to a first interface bus having only six or less communication lines and coupled to a second interface bus having a larger number of communication lines than the first interface bus. The wrapper can communicate first signals with the link controller over the first interface bus and perform conversion between the first signals and second signals communicated on the second interface bus. A core, coupled to the wrapper by the second interface bus, can communicate device signals with the device communication bus by performing conversion between the second signals and the device signals.

Abstract: In an embodiment, an analog front end (AFE) bridge for a SLPI PHY includes: an AFE LINK-side circuit having at least one pair of differential LINK-side nodes which does not conform to SLPI PHY specifications; an AFE PHY-side circuit having a pair of differential PHY-side nodes conforming to SLPI PHY specifications, wherein the AFE PHY-side circuit is coupled to the AFE LINK-side circuit; and a termination control circuit coupled to the AFE PHY-side circuit. A method of bridging a legacy LINK circuit to a SLPI PHY circuit includes: communicating with a legacy LINK circuit with a legacy LINK protocol; communicating with a SLPI PHY circuit with a SLPY PHY protocol over a differential pair; converting outputs of the legacy LINK circuit into inputs of the SLPI PHY circuit; converting outputs of the SLPI PHY circuit into inputs of the legacy LINK circuit; controlling a termination of the differential pair.

Abstract: A system for driving columns of a liquid crystal display includes logic circuitry operating in a supply path between a first and a second supply voltage in which the first supply voltage is higher than the second supply voltage. The logic circuitry is capable of generating first logic signals and second logic signals whose value is equal to the first or second supply voltage. The system includes two level shifters coupled to the logic circuitry and operating in a supply path between a third supply voltage greater than the first supply voltage and the second supply voltage; the level shifters are capable of raising the value of the second logic signals. The system also includes a first and a second pair of transistors having different supply paths and having an output terminal in common; the first and the second pair of transistors are coupled to the level shifters to determine the drive signal of a column.

Abstract: A system for driving columns of a liquid crystal display includes logic circuitry operating in a supply path between a first and a second supply voltage in which the first supply voltage is higher than the second supply voltage. The logic circuitry is capable of generating first logic signals and second logic signals whose value is equal to the first or second supply voltage. The system includes two level shifters coupled to the logic circuitry and operating in a supply path between a third supply voltage greater than the first supply voltage and the second supply voltage; the level shifters are capable of raising the value of the second logic signals. The system also includes a first and a second pair of transistors having different supply paths and having an output terminal in common; the first and the second pair of transistors are coupled to the level shifters to determine the drive signal of a column.

Abstract: A system for driving columns of a liquid crystal display includes logic circuitry operating in a supply path between a first and a second supply voltage in which the first supply voltage is higher than the second supply voltage. The logic circuitry is capable of generating first logic signals and second logic signals whose value is equal to the first or second supply voltage. The system includes two level shifters coupled to the logic circuitry and operating in a supply path between a third supply voltage greater than the first supply voltage and the second supply voltage; the level shifters are capable of raising the value of the second logic signals. The system also includes a first and a second pair of transistors having different supply paths and having an output terminal in common; the first and the second pair of transistors are coupled to the level shifters to determine the drive signal of a column.

Abstract: A method creates a display device driverby steps including: considering transmittance characteristics in relation to voltages applied to plural liquid crystal displays; defining a transmittance curve based on the voltage applied to said displays, for each display; applying a gamma correction, with different values of the gamma exponent, to each transmittance curve; applying a kickback correction to each curve; positioning branch points along said curves; determining a resistance value for each branch point and for each curve for each display; choosing a minimum resistance value for each branch point; choosing a maximum resistance value of for each branch point; calculating the difference between said minimum resistance value and said maximum resistance value for each branch point; defining for each branch point a fixed resistance value equal to said minimum resistance value; defining for each branch point an interval of values for a variable resistance equal to said difference.

Abstract: The present invention describes a system for driving rows of a liquid crystal display including at least one module for driving one single row of the liquid crystal display. The module includes an inverter operating in a supply path between a first and a second supply line of the system, where the first supply line includes a first switch for coupling the inverter to a first or to a second supply voltage and the second supply line includes a second switch for coupling the inverter to a third or to a fourth supply voltage. The inverter is driven by logic circuitry and provides a drive signal for one single row of the liquid crystal display.

Abstract: A method for driving low consumption LCD modules, the LCD modules having a multiplicity of display elements located at the intersections of a matrix having a plurality of row electrodes and a plurality of column electrodes, the method includes the phases of applying an M bit electrical digital signal to at least one row electrode at a time, subdivided in a plurality of time intervals equal to 2M?1, the electrical digital signal suitable for illuminating each of the display elements with a predefined luminosity level chosen from among 2M luminosity levels, each of the M bits is applied for a preset duration, then reducing the preset duration of each of the M bits in accordance with a predefined scale factor K and subdividing the M bits in (2M?1)/K plurality of time intervals.

Abstract: A new memory controller for use in a display, such as a liquid crystal display of the type comprising a set of first drivers, a set of second drivers, a portion of which can be converted to the first drivers, and a RAM memory structured to accept data at an input and output the data to the sets of first and second drivers when a master clock signal is received at the RAM memory. The memory controller includes a clock signal generator structured to generate the master clock signal; and a control signal generator circuit structured to generate control signals for the RAM memory and the sets of first and second drivers.

Abstract: The present invention refers to a method for scanning sequence selection for displays. In one scanning sequence selection for displays having a plurality of rows and columns, the plurality of rows and columns cross each other defining a plurality of optical elements having a first optical state and a second optical state in response to a first electric state and to a second electric state. The method includes the phases of driving the plurality of rows of the display according to a prefixed scanning ordering. The prefixed scanning ordering is predisposed by ordering every column of the columns so that the total switching number between said first electric state and said second electric state is minimized.