Abstract: The present invention relates to a driving method for flat panel display devices, particularly a driving method combining a Multi Line Addressing (MLA) technique and a Frame Rate Control (FRC) technique, for flat panel display devices such as Liquid Crystal Display (LCD).

Abstract: A high-efficiency electronic circuit generates and regulates a supply voltage and includes a charge-pump voltage multiplier which is associated with an oscillator and has an output connected to a voltage regulator in order to ultimately output said supply voltage. Advantageously, the circuit comprises a first hysteresis comparator having as inputs the regulator output and the multiplier output, and comprises a second hysteresis comparator having as inputs a reference potential and a partition of the voltage presented on the regulator output. The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator through a logic circuit to modulate the oscillator operation.

Abstract: A high-efficiency electronic circuit generates and regulates a supply voltage and includes a charge-pump voltage multiplier which is associated with an oscillator and has an output connected to a voltage regulator in order to ultimately output said supply voltage. Advantageously, the circuit comprises a first hysteresis comparator having as inputs the regulator output and the multiplier output, and comprises a second hysteresis comparator having as inputs a reference potential and a partition of the voltage presented on the regulator output. The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator through a logic circuit to modulate the oscillator operation.

Abstract: A new memory controller for use in a display, such as a liquid crystal display of the type comprising a set of first drivers, a set of second drivers, a portion of which can be converted to the first drivers, and a RAM memory structured to accept data at an input and output the data to the sets of first and second drivers when a master clock signal is received at the RAM memory. The memory controller includes a clock signal generator structured to generate the master clock signal; and a control signal generator circuit structured to generate control signals for the RAM memory and the sets of first and second drivers.