Abstract: The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction.

Abstract: A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

Abstract: A method, implementable on a multiple-input, multiple-output symbol receiver, includes selecting a hypothesis for a second symbol value U2 from among the set of fixed constellation points, calculating a hypothesis for a first symbol value U1 from the resultant selected U2 value, and generating a first half of counter-hypotheses from interim results of calculating the hypotheses values.

Abstract: The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt request is from one of a plurality of modules; wherein the interrupt request notifying a writing instruction of a first data by the one of the plurality of modules to a shared memory; and wherein the shared memory is accessible to the plurality of modules through a shared bus; suspending the interrupt request; validating a completion of an execution of the writing instruction; wherein the validating is performed after the suspending; and resuming the interrupt request after the completion of the execution of the writing is validated, whereby to notify a to the CPU about the completion of the execution of the writing instruction.

Abstract: A method, implementable on a multiple-input, multiple-output symbol receiver, includes selecting a hypothesis for a second symbol value U2 from among the set of fixed constellation points, calculating a hypothesis for a first symbol value U1 from the resultant selected U2 value, and generating a first half of counter-hypotheses from interim results of calculating the hypotheses values.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.

Abstract: A class D amplifier is provided. The class D amplifier includes an interpolator, a sampling rate converter, a pulse width modulator, a sigma-delta modulator, and a pulse width modulation (PWM) pulse generator (PPG). The sampling rate converter interpolates the output of the interpolator such that the sampling rate converter up-samples the interpolator output by a factor that is greater than one and less than two. The pulse width modulator outputs a multi-bit digital signal. The sigma-delta modulator performs sigma-delta modulation on the pulse width modulator output, the order of the sigma-delta modulation is programmable, and the output of the sigma-delta modulator is a multi-bit, digital signal. At least one of the orders to which the sigma-delta modulator can be programmed is greater than two. The PPG provides a pulse signal such that the width of each pulse is based on the value of the sigma-delta modulator output.

Abstract: A class D amplifier is provided. The class D amplifier includes an interpolator, a sampling rate converter, a pulse width modulator, a sigma-delta modulator, and a pulse width modulation (PWM) pulse generator (PPG). The sampling rate converter interpolates the output of the interpolator such that the sampling rate converter up-samples the interpolator output by a factor that is greater than one and less than two. The pulse width modulator outputs a multi-bit digital signal. The sigma-delta modulator performs sigma-delta modulation on the pulse width modulator output, the order of the sigma-delta modulation is programmable, and the output of the sigma-delta modulator is a multi-bit, digital signal. At least one of the orders to which the sigma-delta modulator can be programmed is greater than two. The PPG provides a pulse signal such that the width of each pulse is based on the value of the sigma-delta modulator output.

Abstract: A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

Abstract: A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory by detecting in hardware an error based on one of three selectable modes of error detection and correction; and correcting the error by executing error correction software corresponding to the selected mode of error detection and correction.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applying error correction information stored in the cache corresponding to the accessed PBN to correct the data error.

Abstract: Systems and methods are disclosed to detect and correct errors in a flash memory by detecting in hardware an error based on one of three selectable modes of error detection and correction; and correcting the error by executing error correction software corresponding to the selected mode of error detection and correction.

Abstract: Systems and methods are disclosed to perform fast discrete cosine transform (DCT) by computing the DCT in five stages using three coefficients, and scaling the outputs using a plurality of scaling coefficients.

Abstract: A highly integrated, single chip computer system having not only a central-processing unit (CPU) but also specialized coprocessors. The specialized coprocessors, for example, enable the single chip computer system to be reasonably sized, yet perform high quality video (e.g., MPEG-2) and graphics operations (e.g., three-dimensional graphics). The single chip computer system offers improved performance of video and graphics operations, resource scheduling and security. The improved security offered by the single chip computer system enables program code or data stored external to the single chip computer system to be encrypted so as to hinder unauthorized access, while internal to the single chip computer system the program code or data is decrypted. The single chip computer system is particularly suitable for video game consoles having high quality graphics and/or video, digital video disk (DVD) players, and set-top boxes.

Abstract: An MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes motion compensation logic which analyzes motion vectors in an encoded frame of the MPEG stream and uses prior decoded reference blocks to recreate the data encoded by the motion vector. The MPEG decoder stores reference block data according to a novel skewed tile arrangement to minimize the maximum number of page crossings required in retrieving this data from the memory.

Abstract: The present invention addresses the problem of describing an arbitrary object (up to user-defined limits) given a set of triangles with vertex normals describing the object. A novel method of successively merging traingles into larger and larger patches to compute a set of "as-few-as-possible" Bezier patches is presented. This method is not only applicable to arbitrary objects, but also aims at producing as few patches as possible depending on the geometry of the input object. Also presented are methods to enforce C.sup.0 - and C.sup.1 -continuity between a pair of patches B.sub.L (s,t) and B.sub.R (s,t), placed arbitrarily. The methods perturb the appropnate control points to achieve geometric continuities. For C.sup.0 -continuity the area of the hole between the patches is minimized by formulating the area as a series of linear programs, where the continuity has to be enforced across the adjacent boundary curves B.sub.L (1,t) and B.sub.R (0,t). Similarly, to enforce C.sup.