Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die.

Abstract: One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die.

Abstract: Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (?) of tooling impact upon a vertical face the semiconductor device.

Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.