Abstract: A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.

Abstract: A printhead having a number of single-dimensional memristor banks is described. The printhead includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The printhead also includes a number of single-dimensional memristor banks. Each memristor bank includes a number of memristors arranged in a single dimension and a number of serially-connected de-multiplexers to selectively activate a target memristor of the memristor bank. The number of serially-connected de-multiplexers is equal to the number of memristors and an output of at least one de-multiplexer is an input into a subsequent de-multiplexer.

Abstract: A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.

Abstract: A print head with a number of memristors and inverters is described. The print head includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The print head also includes a number of memristor cells. Each memristor cell includes a memristor to store data, a voltage divider serially connected to the 116 memristor cell, and an inverter connected in parallel with the number of memristor cells and the voltage divider.

Abstract: A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.

Abstract: An electronically programmable read-only memory (EPROM) cell includes a semiconductor substrate having source and drain regions; a floating gate, adjacent to the source and drain regions and separated from the semiconductor substrate by a first dielectric layer, the floating gate including: a polysilicon layer formed over the first dielectric layer; a first metal layer electrically connected to the polysilicon layer, where the surface area of the first metal layer is less than 1000 ?m2; and a control gate comprising a second metal layer, capacitively coupled to the first metal layer through a second dielectric material disposed therebetween.

Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells, A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.

Abstract: A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring. The substrate is doped using the polysilicon layer as a mask to form doped regions in the substrate. A dielectric layer is deposited over the polysilicon layer and the substrate. The dielectric layer is etched to expose portions of the polysilicon layer. A metal layer is deposited on the dielectric layer. The metal layer, the dielectric layer, and the exposed portions of the polysilicon layer are etched such that at least a portion of each polysilicon ring is removed.