Patents by Inventor Lequn Liu
Lequn Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250028242Abstract: Embodiments disclosed herein may include a method for developing a photopatterned metal oxo photoresist. In an embodiment, the method may include pre-treating the photopatterned metal oxo photoresist with a pre-treatment process, developing the photopatterned metal oxo photoresist with a thermal dry develop process to selectively remove a portion of the photopatterned metal oxo photoresist and form a resist mask. In an embodiment, the thermal dry develop process includes a first sub-operation, and a second sub-operation that is different than the first sub-operation. In an embodiment, the process further includes post-treating the resist mask with a post-treatment process.Type: ApplicationFiled: October 7, 2024Publication date: January 23, 2025Inventors: TZU SHUN YANG, ZHENXING HAN, MADHUR SACHAN, LEQUN LIU, NASRIN KAZEM, LAKMAL CHARIDU KALUTARAGE, MARK JOSEPH SALY
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Patent number: 12183631Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.Type: GrantFiled: June 14, 2022Date of Patent: December 31, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Suketu Parikh, Alexander Jansen, Joung Joo Lee, Lequn Liu
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Publication number: 20240290883Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.Type: ApplicationFiled: February 14, 2024Publication date: August 29, 2024Applicant: Applied Materials, Inc.Inventors: Sai Hooi Yeong, Hui Zhao, Ashish Pal, El Mehdi Bazizi, Benjamin Colombeau, Balasubramanian Pranatharthiharan, Lequn Liu
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Publication number: 20240272552Abstract: Embodiments disclosed herein include a method of patterning a substrate. In an embodiment, the method comprises, disposing a photoresist layer over a substrate, and exposing the photoresist layer to form an exposed region and an unexposed region in the photoresist layer. In an embodiment, the method further comprises treating either the exposed region or the unexposed region with a sequential infiltration synthesis (SIS) process to form a treated region, and developing the photoresist layer to remove portions of the photoresist layer other than the treated region.Type: ApplicationFiled: January 9, 2024Publication date: August 15, 2024Inventors: GABRIELA ALVA, ZHENXING HAN, MADHUR SACHAN, CHI-I LANG, LIN ZHOU, LEQUN LIU, NASRIN KAZEM
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Publication number: 20240160100Abstract: Embodiments disclosed herein may include a method for developing a photopatterned metal oxo photoresist. In an embodiment, the method may include pre-treating the photopatterned metal oxo photoresist with a pre-treatment process, developing the photopatterned metal oxo photoresist with a thermal dry develop process to selectively remove a portion of the photopatterned metal oxo photoresist and form a resist mask. In an embodiment, the thermal dry develop process includes a first sub-operation, and a second sub-operation that is different than the first sub-operation. In an embodiment, the process further includes post-treating the resist mask with a post-treatment process.Type: ApplicationFiled: July 17, 2023Publication date: May 16, 2024Inventors: Tzu Shun Yang, Zhenxing Han, Madhur Sachan, Lequn Liu, Nasrin Kazem, Lakmal Charidu Kalutarage, Mark Joseph Saly
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Publication number: 20240136229Abstract: A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.Type: ApplicationFiled: September 6, 2023Publication date: April 25, 2024Inventors: Jody FRONHEISER, Sai Hooi YEONG, Benjamin COLOMBEAU, Balasubramanian PRANATHARTHIHARAN, Lequn LIU
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Publication number: 20240071773Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.Type: ApplicationFiled: August 11, 2023Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Lei Liao, Yichuan Ling, Zhiyu Huang, Hideyuki Kanzawa, Fenglin Wang, Rajesh Prasad, Yung-Chen Lin, Chi-I Lang, Ho-yung David Hwang, Lequn Liu
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Publication number: 20240038553Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.Type: ApplicationFiled: July 25, 2023Publication date: February 1, 2024Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Balasubramanian Pranatharthiharan, Lequn Liu, Brian K. Kirkpatrick
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Patent number: 11749315Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: GrantFiled: December 15, 2021Date of Patent: September 5, 2023Assignee: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Patent number: 11751382Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.Type: GrantFiled: April 11, 2022Date of Patent: September 5, 2023Assignee: Applied Materials, Inc.Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
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Publication number: 20230178628Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.Type: ApplicationFiled: October 17, 2022Publication date: June 8, 2023Applicant: Applied Materials, Inc.Inventors: Benjamin Colombeau, Balasubramanian Pranatharthiharan, Lequn Liu
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Publication number: 20230005789Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.Type: ApplicationFiled: June 14, 2022Publication date: January 5, 2023Inventors: Suketu PARIKH, Alexander JANSEN, Joung Joo LEE, Lequn LIU
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Publication number: 20230005844Abstract: Interconnect structures on a substrate have low resistivity and high dopant interfaces. In some embodiments, the structures may have an opening with a sidewall from an upper surface to an underlying metallic layer of copper, a barrier layer of tantalum nitride formed on the sidewall of the opening, a liner layer of cobalt or ruthenium formed on the barrier layer and on the underlying metallic layer, a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the opening to form a via-the first dopant content is approximately 0.5 percent to approximately 10 percent, and a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening—the second dopant content is more than zero to approximately 0.5 percent of the dopant and is less than the first dopant content.Type: ApplicationFiled: June 14, 2022Publication date: January 5, 2023Inventors: Suketu PARIKH, Alexander JANSEN, Joung Joo LEE, Lequn LIU
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Patent number: 11454751Abstract: An eye wear comprises an optical filter disposed in front of an eye. The optical filter has a transmittance function of wavelength comprising a transmittance peak having a peak transmittance and a transmittance bandwidth. A transmittance outside the transmittance peak is at a lower level transmittance, wherein a ratio of the lower level transmittance to the peak transmittance is less than unity. The transmittance peak is at a central wavelength of a laser that emits laser light forming one of a laser spot and a laser line. The transmittance bandwidth is larger than a bandwidth of the laser light emitted by the laser. The laser spot or the laser line formed by the laser light emitted by the laser is viewed through the eye wear.Type: GrantFiled: May 4, 2019Date of Patent: September 27, 2022Inventors: Suganda Jutamulia, Lequn Liu
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Publication number: 20220238533Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.Type: ApplicationFiled: April 11, 2022Publication date: July 28, 2022Applicant: Applied Materials, Inc.Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
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Patent number: 11329052Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.Type: GrantFiled: July 27, 2020Date of Patent: May 10, 2022Assignee: Applied Materials, Inc.Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
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Publication number: 20220108728Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Patent number: 11295786Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: GrantFiled: February 3, 2020Date of Patent: April 5, 2022Assignee: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Publication number: 20220013624Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Applicant: Micromaterials LLCInventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu
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Patent number: D972505Type: GrantFiled: June 16, 2022Date of Patent: December 13, 2022Inventor: Lequn Liu