Abstract: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.

Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.

Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.

Abstract: A method for determining the optimum time at which a plasma etching operation should be terminated. The optical emission intensity (S.sub.1) of the plasma in a narrow band centered about a predetermined spectral line, indicative of the gas phase concentration of a plasma etch product or reactant species. The optical emission intensity (S.sub.2) of the plasma in a wide band centered about the predetermined spectral line, indicative of a background emission signal is also monitored. The intensity (S.sub.1L) of the spectral line is then determined in accordance with the equation S.sub.1L =S.sub.1 -k (.alpha.S.sub.2 -S.sub.1). The etching process is terminated when the monitored signal intensity (S.sub.1L) or its time derivative reaches a predetermined value.