Abstract: Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the minimum clock periods are determined from detailed timing analyses after the placement and routing for the module; and, in retiming the circuit that contains the module, a data flow graph representation of the module is constructed based on the target clock period of the circuit and the correlation between the latencies and the minimum clock periods. In at least one embodiment of the present invention, hierarchical retiming is performed in which portions of the circuit is retimed to generate results (e.g., for different latencies), which are selectively used for the retiming of the entire circuit based on the target clock period.

Abstract: Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the minimum clock periods are determined from detailed timing analyses after the placement and routing for the module; and, in retiming the circuit that contains the module, a data flow graph representation of the module is constructed based on the target clock period of the circuit and the correlation between the latencies and the minimum clock periods. In at least one embodiment of the present invention, hierarchical retiming is performed in which portions of the circuit is retimed to generate results (e.g., for different latencies), which are selectively used for the retiming of the entire circuit based on the target clock period.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

Abstract: Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the minimum clock periods are determined from detailed timing analyses after the placement and routing for the module; and, in retiming the circuit that contains the module, a data flow graph representation of the module is constructed based on the target clock period of the circuit and the correlation between the latencies and the minimum clock periods. In at least one embodiment of the present invention, hierarchical retiming is performed in which portions of the circuit is retimed to generate results (e.g., for different latencies), which are selectively used for the retiming of the entire circuit based on the target clock period.

Abstract: Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

Abstract: A method and corresponding apparatus for selecting a sequence of quantization parameter values in a video encoder, the video encoder being arranged to encode a video frame as a sequence of n macroblocks and to assign a quantization parameter value for each macroblock of the video frame. The method includes steps (23 24 25) in which quantization parameter values assigned to at least a subset of said sequence of n macroblocks are optimized in such a way as to minimize a cost associated with their encoding.

Abstract: Apparatus, and an associated method, for facilitating communication of a vector graphic representation, or other content, pursuant to effectuation of a communication service. The content forms, for instance, an animated graphic, such as that used in a mobile communication application to effectuate an animated multi-media message. The vector graphic is encoded according to codewords that function to compress the data prior to its communication upon a radio link. And, once delivered to a receiving station, a decoder decodes the content into unencoded form. Codebooks are utilized and accessed by an encoder and decoder of a sending/receiving station pair.

Abstract: A method and corresponding apparatus for selecting a sequence of quantization parameter values in a video encoder, the video encoder being arranged to encode a video frame as a sequence of n macroblocks and to assign a quantization parameter value for each macroblock of the video frame. The method includes steps (23 24 25) in which quantization parameter values assigned to at least a subset of said sequence of n macroblocks are optimized in such a way as to minimize a cost associated with their encoding.

Abstract: A motion estimation system for a video coder is disclosed. The system comprises an input for a video image (6) to be coded. It also comprises a series of motion estimators (2, 3) of varying complexity, for estimating a motion vector field between the received image (6) and a reference image (5). The subsequent motion estimator in the series is selected by a control means (4) if a prediction error associated with the motion vector field estimated by the currently selected motion estimator exceeds a predetermined threshold.

Abstract: Apparatus, and an associated method, for facilitating communication of a vector graphic representation, or other content, pursuant to effectuation of a communication service. The content forms, for instance, an animated graphic, such as that used in a mobile communication application to effectuate an animated multi-media message. The vector graphic is encoded according to codewords that function to compress the data prior to its communication upon a radio link. And, once delivered to a receiving station, a decoder decodes the content into unencoded form. Codebooks are utilized and accessed by an encoder and decoder of a sending/receiving station pair.

Abstract: A motion estimation system for a video coder has an input for a video image to be coded, and includes a series of motion estimators of varying complexity for estimating a motion vector field between a received image and a reference image. The estimation is accomplished by sequential use of the estimators, wherein a subsequent estimator of the sequence is selected by a controller based on a prediction error, associated with the motion vector field estimated by a currently selected estimator, exceeding a predetermined threshold.

Abstract: This invention relates to a system for compression of video sequences that is using motion compensated prediction. The key part of such system is motion vector field coding. The goal of motion vector field coding is to minimize the number of bits necessary for representation of the motion vector field while retaining at the same time very low prediction error. This invention discloses new matrix operations in the motion analyzer of the motion field coder.

Abstract: A motion estimation system for a video coder is disclosed. The system comprises an input for a video image (6) to be coded. It also comprises a series of motion estimators (2, 3) of varying complexity, for estimating a motion vector field between the received image (6) and a reference image (5). The subsequent motion estimator in the series is selected by a control means (4) if a prediction error associated with the motion vector field estimated by the currently selected motion estimator exceeds a predetermined threshold.