Patents by Inventor Li Chen

Li Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118715
    Abstract: Compact packages including microelectromechanical system (MEMS) devices and multiple application specific integrated circuits (ASICs) are described. These packages are sufficiently small to be applicable to contexts in which space requirements are particularly strict, such as in consumer electronics. These packages involve vertical die stacks. A first ASIC may be positioned on one side of the die stack and another ASIC may be positioned on the other side of the die stack. A die including a MEMS device (e.g., an accelerometer, gyroscope, switch, resonator, optical device) is positioned between the ASICs. Optionally, an interposer serving as cap substrate for the MEMS device is also positioned between the ASICs. In one example, a package of the types described herein has an extension of 2 mm×2 mm in the planar axes and less than 500-800 ?m in height.
    Type: Application
    Filed: January 24, 2023
    Publication date: April 10, 2025
    Applicant: Analog Devices, Inc.
    Inventors: Xin Zhang, Jianglong Zhang, Li Chen, John C. Cowles, Michael Judy, Shafi Saiyed
  • Publication number: 20250118666
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Inventors: TZU PEI CHEN, MIN-HSUAN LU, HAO-HENG LIU, YUTING CHENG, HSU-KAI CHANG, PO-CHIN CHANG, OLIVIA PEI-HUA LEE, SHENG-TSUNG WANG, HUAN-CHIEH SU, SUNG-LI WANG, PINYEN LIN
  • Publication number: 20250120090
    Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The method comprises forming an array device semiconductor structure comprising an alternating conductor/dielectric stack disposed on a semiconductor layer, and an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The method further comprises a peripheral device disposed on a substrate, and a peripheral interconnect layer disposed on the peripheral device and including a second interconnect structure and a pad. The pad is electrically connected with the peripheral device through the second interconnect structure. The method further comprises bonding the array interconnect layer to the peripheral interconnect layer, such that the first interconnect structure is joined with the second interconnect structure. The method further comprises forming a pad opening exposing a surface of the pad.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventors: Jun CHEN, Zhiliang XIA, Li Hong XIAO
  • Publication number: 20250118373
    Abstract: The present disclosure relates to methods and devices for memory erase. In one example, a method for operating a memory device includes increasing a voltage of a source line (SL) coupled to a memory string from an initial voltage at a beginning of a time period, where the voltage of the SL is increased to an erase voltage at an end of the time period. The memory device can apply a first voltage to a first word line (WL) before the end of the time period. The memory device can apply a second voltage to a second WL adjacent to the first WL before the end of the time period. The memory device can further apply a third voltage to the second WL no later than the end of the time period, where the third voltage is higher than the second voltage.
    Type: Application
    Filed: November 22, 2023
    Publication date: April 10, 2025
    Inventors: Li XIANG, Zhuo CHEN
  • Publication number: 20250115617
    Abstract: The disclosure provides a method of preparing chiral metacyclophanes. The method involves palladium-catalyzed cross-coupling of a meta-substituted aryl group with base and a chiral ligand. The disclosure also provides metacyclophane compounds, which include diaryl and monoaryl macrocycles.
    Type: Application
    Filed: September 20, 2024
    Publication date: April 10, 2025
    Inventors: Junqi Li, Shengkai Wei, Liang-Yu Chen
  • Publication number: 20250115483
    Abstract: A method for manufacturing a humidity alarm device based on laser-induced graphene is performed as follows. Carbon-based films are coated with a hydroxide ion-containing solution and processed by a laser device to generate hydrophilic graphene layers. The hydrophilic graphene layers are peeled off from the carbon-based films, wetted, and respectively wrapped around shaping rods varying in diameter. The wrapped rods are heated and shaped by a drying oven to obtain curled graphene switches. Each curled graphene switch is connected in series with an alarm lamp to form an alarm component. The alarm components are connected in parallel, and then connected to a positive terminal and a negative terminal of a power supply to form the humidity alarm device.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Yun CHEN, Bin XIE, Yuanhui GUO, Hao ZHANG, Maoxiang HOU, Li MA, Xin CHEN
  • Publication number: 20250118690
    Abstract: A semiconductor package includes: a die having a conductive pad at a first side of the die; and a redistribution structure over the first side of the die and electrically coupled to the die. The redistribution structure includes: a first dielectric layer including a first dielectric material; a first via in the first dielectric layer, where the first via is electrically coupled to the conductive pad of the die; and a first dielectric structure embedded in the first dielectric layer, where the first dielectric structure includes a second dielectric material different from the first dielectric material, where the first dielectric structure laterally surrounds the first via and contacts sidewalls of the first via.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Wen-Yi Lin, Kan-Ju Yang, Kai-Cheng Chen, Chien-Li Kuo, Chien-Chen Li
  • Patent number: 12272726
    Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
  • Patent number: 12273768
    Abstract: Embodiments of the present disclosure provide a medium access control protocol data unit (MAC PDU) processing method, a terminal and a medium. The method includes: a terminal determining a preorganized MAC PDU that needs to be transmitted on a subsequent resource; updating, with latest uplink control information, content of a media access control control element (MAC CE) in an MAC subPDU corresponding to the MAC CE in the preorganized MAC PDU.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: April 8, 2025
    Assignee: DATANG MOBILE COMMUNICATIONS EQUIPMENT CO., LTD.
    Inventors: Li Chen, Jinhua Miao, Pierre Bertrand
  • Patent number: 12269807
    Abstract: The invention relates to crystalline forms of the bis-HCl salt of a compound represented by Structural Formula 1, and pharmaceutical compositions comprising crystalline forms of the bis-HCL salt of a compound represented by Structural Formula 1 described herein. The crystalline forms of the bis-HCl salt of a compound of Structural Formula 1 and compositions comprising the crystalline forms of the compound of Structural Formula 1 provided herein, in particular, crystalline Form I, crystalline Form J, crystalline Form A, and crystalline Form B, or mixtures thereof, can be incorporated into pharmaceutical compositions, which can be used to treat various disorders. Also described herein are methods for preparing the crystalline forms (e.g., Forms I, J, B and A) of the bis-HCl salt of a compound represented by Structural Formula 1.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: April 8, 2025
    Assignee: Tetraphase Pharmaceuticals, Inc.
    Inventors: Danny LaFrance, Philip C. Hogan, Yansheng Liu, Minsheng He, Chi-Li Chen, John Niu
  • Patent number: 12272603
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Chih-Liang Chen, Tzu-Chiang Chen, I-Sheng Chen, Lei-Chun Chou
  • Patent number: 12271520
    Abstract: In some embodiments, an electronic device optionally identifies a person's face, and optionally performs an action in accordance with the identification. In some embodiments, an electronic device optionally determines a gaze location in a user interface, and optionally performs an action in accordance with the determination. In some embodiments, an electronic device optionally designates a user as being present at a sound-playback device in accordance with a determination that sound-detection criteria and verification criteria have been satisfied. In some embodiments, an electronic device optionally determines whether a person is further or closer than a threshold distance from a display device, and optionally provides a first or second user interface for display on the display device in accordance with the determination. In some embodiments, an electronic device optionally modifies the playing of media content in accordance with a determination that one or more presence criteria are not satisfied.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: April 8, 2025
    Assignee: Apple Inc.
    Inventors: Avi E. Cieplinski, Jeffrey Traer Bernstein, Julian Missig, May-Li Khoe, Bianca Cheng Costanzo, Myra Mary Haggerty, Duncan Robert Kerr, Bas Ording, Elbert D. Chen
  • Publication number: 20250113696
    Abstract: A display substrate, a display panel, and preparation methods thereof. The display substrate includes a base substrate, a bonding pad, and an insulating layer. The bonding pad is located on one side of the base substrate and includes at least two bonding pad layers stacked in a thickness direction of the base substrate. The insulating layer is located between adjacent two of the bonding pad layers, and the insulating layer includes a via. In adjacent two of the bonding pad layers, the bonding pad layer on the side away from the base substrate extends into the via and is electrically connected to the bonding pad layer on the side close to the base substrate.
    Type: Application
    Filed: December 10, 2024
    Publication date: April 3, 2025
    Applicant: Chengdu Vistar Optoelectronics Co., Ltd.
    Inventors: Li HE, Xiuqi HUANG, Xuan CAO, Yunlei CHEN, Xiaolong ZHANG
  • Publication number: 20250109010
    Abstract: A MEMS die comprises a substrate having an opening, a diaphragm attached to the substrate around a periphery of the opening so as to cover the opening, the diaphragm having an aperture, and a backplate separated from the diaphragm and disposed on a side of the diaphragm opposite the substrate, the backplate comprising a plug that extends toward the aperture from an attached end to a free end. In an embodiment the free end of the plug has a smaller area than the aperture, and the plug is separated from the diaphragm by a gap, wherein a size of the gap determines a level of fluid communication across the diaphragm through the aperture.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Inventors: Faisal Zaman, Sung B. Lee, Richard Li-Chen Chen, Shubham Shubham, Michael Kuntzman, Michael Pedersen
  • Publication number: 20250109972
    Abstract: A sensing module of a sensor package includes a substrate and a sensor. The substrate includes an insulating layer, an integrated circuit (IC), a plurality of first circuits, and a plurality of second circuits. The IC is embedded in the insulating layer and includes a plurality of first contacts and a plurality of second contacts. The first circuits are respectively connected to the first contacts, and a part of each of the first circuits is exposed from the first surface of the insulating layer and is defined as a connection pad. The second circuits are respectively connected to the second contacts, and a part of each of the second circuits is exposed from the second surface of the insulating layer and is defined as a soldering pad. The sensor is disposed on the first surface of the insulating layer and is electrically coupled to the first circuits.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 3, 2025
    Inventors: GUANG-LI SONG, WUI-PIN LEE, SIN-HENG LIM, HENG-CHANG CHEN
  • Publication number: 20250112032
    Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventors: Tsung-Jen YANG, Yi-Zhen CHEN, Chih-Pin WANG, Chao-Li SHIH, Ching-Hou SU, Cheng-Yi HUANG
  • Publication number: 20250111639
    Abstract: This invention provides a method for detecting object, which comprises receiving an image; and executing a deep neural network architecture for the image to obtain one or more object bounding box, wherein the deep neural network architecture comprises a two-dimensional discrete wavelet transform.
    Type: Application
    Filed: September 3, 2024
    Publication date: April 3, 2025
    Inventors: Jun-Yao Zhong, Bo-Yu Chen, Jui-Li Chen, Tse-Min Chen
  • Publication number: 20250111827
    Abstract: A display substrate includes a plurality of data lines extending in a first direction, and a plurality of sub-pixels. A sub-pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes a current control circuit, and a duration control circuit electrically connected to the current control circuit and the light-emitting device. The current control circuit is configured to generate a driving signal to drive the light-emitting device to emit light; and the duration control circuit is configured to generate a duration control signal to control a duration of a connection between the current control circuit and the light-emitting device. The current control circuit and the duration control circuit are electrically connected to a same data line.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventors: Li XIAO, Seungwoo HAN, Dongni LIU, Haoliang ZHENG, Minghua XUAN, Jiao ZHAO, Liang CHEN, Xiaorong CUI
  • Publication number: 20250108979
    Abstract: An inspection system includes a conveying mechanism, a pushing mechanism, a positioning mechanism and an inspection mechanism. The conveying mechanism is configured to convey an object to be inspected. The pushing mechanism is suitable for pushing the object to be inspected in a conveying direction of the conveying mechanism, so as to push the object to be inspected to a first positioning plane and a second positioning plane. The positioning mechanism includes a positioning portion. The positioning portion may move in the conveying direction of the conveying mechanism, so as to define the first positioning plane and the second positioning plane. The object to be inspected abuts against the positioning portion on the first positioning plane and the second positioning plane. The inspection mechanism is suitable for inspecting the object to be inspected when the object to be inspected is located on the first positioning plane and the second positioning plane.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 3, 2025
    Inventors: Zhiqiang CHEN, Li ZHANG, Liang LI, Mingzhi HONG, Zinan WANG, Lei XIE, Ming CHANG
  • Publication number: 20250112155
    Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Scott Clendenning, Feras Eid, Robert Jordan, Wenhao Li, Jiun-Ruey Chen, Tayseer Mahdi, Carlos Felipe Bedoya Arroyave, Shashi Bhushan Sinha, Anandi Roy, Tristan Tronic, Dominique Adams, William Brezinski, Richard Vreeland, Thomas Sounart, Brian Barley, Jeffery Bielefeld