Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A method includes forming fin structures upwardly extending above a semiconductor substrate; conformally depositing a first dielectric layer over the fin structures; depositing a flowable oxide over the first dielectric layer and between the fin structures; performing, at a temperature lower than about 500° C., a steam annealing process on the flowable oxide to cure the flowable oxide; after performing the steam annealing process, etching the cured flowable oxide until a top surface of the cured flowable oxide is lower than top surfaces of the fin structures; forming a second dielectric layer over the cured flowable oxide; forming a first gate structure extending across a first one of the fin structures and a second gate structure extending across a second one of the fin structures; forming first sources/drain regions on the first one of the fin structures and second sources/drain regions on the second one of the fin structures.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract: A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals.

Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle.

Abstract: A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals.