Abstract: A chip package structure includes a flexible substrate, a patterned circuit layer, a fingerprint sensor chip, a plurality of bumps, a patterned dielectric layer and an encapsulant layer. The patterned circuit layer disposed on the flexible substrate includes a fingerprint sensing circuit and a plurality of terminals. The fingerprint sensor chip disposed on the flexible substrate is electrically connected to the fingerprint sensing circuit and includes an active surface, a back surface, and a plurality of bonding pads disposed on the active surface. The bumps disposed between the fingerprint sensor chip and the patterned circuit layer electrically connect the bonding pads and the terminals. The patterned dielectric layer including a first surface and a second surface having a fingerprint sensing region at least covers the fingerprint sensing circuit with the first surface. The encapsulant layer is filled between the flexible substrate and the fingerprint sensor chip and covers the bumps.

Abstract: Automatic trading of virtual characters in online applications comprises publishing virtual characters by a first user in a trading system that involves verification at an application server and locking of the selected virtual characters at the application server. This can ensure that the trading of virtual characters is true, reliable and prompt, and reduces the loss to users arising from the trading of virtual characters.

Abstract: Nonvolatile memory cells (110) are connected to a bitline (BL 170). The bitline is also connected to a source/drain region (620) of a transistor (610), a Y multiplexer transistor for example. This source/drain region is exposed to a higher voltage, and hence is made to have a higher junction breakdown voltage, than the other source/drain region (630) of the same transistor. A nonvolatile memory has a plurality of memory arrays (106), a global decoder (438) and secondary decoders (440). The selection signals provided by the global decoder to the secondary decoders for selecting the control gate lines (140) and the source lines (152) are carried by lines (450) running in the row direction. These signals are low voltage signals (between 0V and Vcc). The super high voltages are carried by lines (460) extending in the column direction to reduce noise injection into the control gate lines, source lines, and wordlines (150), and to reduce the parasitic capacitance associated with the super high voltage lines.

Abstract: In some embodiments, of the present invention, data are written to a plurality of nonvolatile memory cells (Q0, Q15) as follows. A data writing signal is supplied to one of the memory cells (Q0) but not to both of the memory cells. Then data writing signals are supplied to both of the memory cells simultaneously.

Abstract: A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

Abstract: A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.

Abstract: Nonvolatile memory cells (110) are connected to a bitline (BL 170). The bitline is also connected to a source/drain region (620) of a transistor (610), a Y multiplexer transistor for example. This source/drain region is exposed to a higher voltage, and hence is made to have a higher junction breakdown voltage, than the other source/drain region (630) of the same transistor. A nonvolatile memory has a plurality of memory arrays (106), a global decoder (438) and secondary decoders (440). The selection signals provided by the global decoder to the secondary decoders for selecting the control gate lines (140) and the source lines (152) are carried by lines (450) running in the row direction. These signals are low voltage signals (between 0V and Vcc). The super high voltages are carried by lines (460) extending in the column direction to reduce noise injection into the control gate lines, source lines, and wordlines (150), and to reduce the parasitic capacitance associated with the super high voltage lines.

Abstract: In some embodiments, of the present invention, data are written to a plurality of nonvolatile memory cells (Q0, Q15) as follows. A data writing signal is supplied to one of the memory cells (Q0) but not to both of the memory cells. Then data writing signals are supplied to both of the memory cells simultaneously.

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.

Abstract: A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

Abstract: A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.

Abstract: A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments are also provided.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: A nonvolatile memory array can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells of the array in parallel.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.