Abstract: An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off.

Abstract: In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

Abstract: A dynamic random access memory generates an internal power supply voltage IVCC. IVCC is lower in magnitude than the external power supply voltage EVCC. During a read operation, the sense amplifiers are powered from EVCC while the bit lines charge to their output levels. Then the sense amplifiers stop being powered from EVCC and begin being powered from IVCC to maintain the bit lines at their output levels. A timer defines the time that the sense amplifiers are powered from EVCC. This time depends inversely on EVCC. The timer includes a transistor connected between EVCC and an input of the inverter. The time that the sense amplifiers are powered from EVCC is defined by the time that the input of the inverter charges to the trip point of the inverter.

Abstract: A sense amplifier charging circuit can work with different power supply voltages (EVCC). When EVCC is high, a signal generated from EVCC disables some of the charging transistors to reduce the circuit noise. When EVCC is low, the signal generated from EVCC enables the transistors thus increasing the circuit speed.

Abstract: A DRAM has a sensing circuit which includes an on-chip capacitors having a total capacitance greater than about 35% of the total capacitance of the bit lines. The on-chip capacitors are coupled to a power line of the sense amplifiers and stabilizes a power supply voltage to prevent voltage drop and noise during the large sensing currents for a read/refresh cycle. A read/refresh cycle in accordance with an embodiment of the invention includes precharging bit lines and the on-chip capacitors before connecting memory transistors to the bit lines and connecting power to the sense amplifiers. Capacitors can be formed in any available space in the integrated circuit particularly in space under metal bus lines in peripheral circuitry surrounding a memory array.

Abstract: A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

Abstract: A logical latch is permanently programmable to a selected state for use as a control circuit with extremely low power consumption in an integrated circuit.

Abstract: An integrated circuit memory device is provided which includes a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of y-lines; an address bus including a first bus oriented with a y-dimension and a second bus oriented with an x-dimension; and x-address generator; a y-address generator; a multiplexer circuit for operatively coupling one of the x-address generator and the y-address generator to the address bus; a plurality of y-address decoders each for producing decoded y-information to at least one of the plurality of y-lines; a plurality of separate x-address decoders each for producing decoded x-information for at least one of the plurality of x-lines; and a plurality of separate sustain circuits each for sustaining decoded x-information produced by at least one x-decoder.