Patents by Inventor Li-Chun Liang
Li-Chun Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140047300Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.Type: ApplicationFiled: October 28, 2012Publication date: February 13, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Li-Chun Liang, Tien-Ching Wang, Kuo-Hsin Lai
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Patent number: 8595594Abstract: A data processing method is provided. A data is compressed to obtain a compressed data. Compression information corresponding to the compressed data is obtained. Error checking and correcting (ECC) codes are respectively generated for the compression information and the compressed data. The compression information, the compressed data, and the ECC codes are respectively written into a rewritable non-volatile memory module. The compression information, the compressed data, and the ECC codes are respectively read from the rewritable non-volatile memory module. An ECC procedure is preformed on the compression information according to the corresponding ECC code, so as to obtain a storage state when the compression information is written. An ECC procedure is preformed on the compressed data according to the storage state of the compression information and the ECC code corresponding to the compressed data, so as to obtain a storage state when the compressed data is written.Type: GrantFiled: August 18, 2011Date of Patent: November 26, 2013Assignee: Phison Electronics Corp.Inventor: Li-Chun Liang
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Patent number: 8392797Abstract: An error correcting controller for connecting an old host controller having an old error correcting function with a new flash memory which requires a new error correcting function is provided. When the old host controller needs to write data into the new flash memory, the error correcting controller generates a new error correcting code according to the new error correcting function for the data. Then, when the old host controller needs to read the data from the new flash memory, the error correcting controller performs an error correcting procedure according to the new error correcting code and transmits information to the old host controller according to the result of the error correcting procedure and the old error correcting function. Accordingly, it is possible to allow the old host controller to access the new flash memory without changing the architecture of the old host controller.Type: GrantFiled: January 23, 2009Date of Patent: March 5, 2013Assignee: Phison Electronics Corp.Inventors: Kuo-Yi Cheng, Li-Chun Liang, Chien-Hua Chu
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Patent number: 8386860Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.Type: GrantFiled: May 27, 2010Date of Patent: February 26, 2013Assignee: Phison Electronics Corp.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai, Li-Chun Liang
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Publication number: 20130019138Abstract: A data processing method is provided. A data is compressed to obtain a compressed data. Compression information corresponding to the compressed data is obtained. Error checking and correcting (ECC) codes are respectively generated for the compression information and the compressed data. The compression information, the compressed data, and the ECC codes are respectively written into a rewritable non-volatile memory module. The compression information, the compressed data, and the ECC codes are respectively read from the rewritable non-volatile memory module. An ECC procedure is preformed on the compression information according to the corresponding ECC code, so as to obtain a storage state when the compression information is written. An ECC procedure is preformed on the compressed data according to the storage state of the compression information and the ECC code corresponding to the compressed data, so as to obtain a storage state when the compressed data is written.Type: ApplicationFiled: August 18, 2011Publication date: January 17, 2013Applicant: PHISON ELECTRONICS CORP.Inventor: Li-Chun Liang
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Patent number: 8276033Abstract: A data writing method for a flash memory, and a flash memory controller and a flash memory storage apparatus using the same are provided. First, data is received from a host system. Next, the data is divided into at least one frame. Afterwards, an error checking and correcting (ECC) code corresponding to the frame is generated so as to form at least one ECC frame. Then, the ECC frame is divided into a plurality of frame segments. Finally, the frame segments are written into a flash memory chip according to a non-sequentially ranking order.Type: GrantFiled: February 12, 2010Date of Patent: September 25, 2012Assignee: Phison Electronics Corp.Inventors: Chien-Fu Tseng, Yu-Hung Liu, Li-Chun Liang, Chih-Kang Yeh
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Publication number: 20120173955Abstract: A data writing method for a rewritable non-volatile memory module is provided. The present method includes compressing an original data to generate a first data and determining whether the length of the first data is smaller than a predetermined length. The present method also includes outputting the first data as a compressed data when the length of the first data is not smaller than the predetermined length. The present method further includes generating an ECC code corresponding to the compressed data, generating an ECC frame according to the compressed data and the ECC code, and writing the ECC frame into the rewritable non-volatile memory module. Accordingly, when data corresponding to the original data is read from the rewritable non-volatile memory module, error bits in the data can be corrected and the original data can be restored according to the ECC code.Type: ApplicationFiled: March 25, 2011Publication date: July 5, 2012Applicant: PHISON ELECTRONICS CORP.Inventor: Li-Chun Liang
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Patent number: 8062487Abstract: A wafer supporting device of a sputter apparatus includes a pedestal positioned in a sputtering chamber and used to load a wafer for sputtering, a deposition ring having a recess positioned on a peripheral portion of the pedestal, and a cover ring positioned on the pedestal and the deposition ring. The cover ring has a gate corresponding to the recess.Type: GrantFiled: June 25, 2007Date of Patent: November 22, 2011Assignee: United Microelectronics Corp.Inventors: Chi-Piao Cheng, Li-Chun Liang, Yu-Jen Huang, Been Chen, Sheng-Yih Ting
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Publication number: 20110258495Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.Type: ApplicationFiled: May 27, 2010Publication date: October 20, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Tseng, Kuo-Hsin Lai, Li-Chun Liang
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Patent number: 7975096Abstract: A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.Type: GrantFiled: August 25, 2008Date of Patent: July 5, 2011Assignee: Phison Electronics Corp.Inventors: Jiunn-Yeong Yang, Chien-Hua Chu, Kuo-Yi Cheng, Li-Chun Liang, Chih-Kang Yeh
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Publication number: 20110154162Abstract: A data writing method for a flash memory, and a flash memory controller and a flash memory storage apparatus using the same are provided. First, data is received from a host system. Next, the data is divided into at least one frame. Afterwards, an error checking and correcting (ECC) code corresponding to the frame is generated so as to form at least one ECC frame. Then, the ECC frame is divided into a plurality of frame segments. Finally, the frame segments are written into a flash memory chip according to a non-sequentially ranking order.Type: ApplicationFiled: February 12, 2010Publication date: June 23, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Fu Tseng, Yu-Hung Liu, Li-Chun Liang, Chih-Kang Yeh
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Publication number: 20100125772Abstract: An error correcting controller for connecting an old host controller having an old error correcting function with a new flash memory which requires a new error correcting function is provided. When the old host controller needs to write data into the new flash memory, the error correcting controller generates a new error correcting code according to the new error correcting function for the data. Then, when the old host controller needs to read the data from the new flash memory, the error correcting controller performs an error correcting procedure according to the new error correcting code and transmits information to the old host controller according to the result of the error correcting procedure and the old error correcting function. Accordingly, it is possible to allow the old host controller to access the new flash memory without changing the architecture of the old host controller.Type: ApplicationFiled: January 23, 2009Publication date: May 20, 2010Applicant: PHISON ELECTRONICS CORP.Inventors: Kuo-Yi Cheng, Li-Chun Liang, Chien-Hua Chu
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Publication number: 20090300271Abstract: A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.Type: ApplicationFiled: August 25, 2008Publication date: December 3, 2009Applicant: PHISON ELECTRONICS CORP.Inventors: Jiunn-Yeong Yang, Chien-Hua Chu, Kuo-Yi Cheng, Li-Chun Liang, Chih-Kang Yeh
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Publication number: 20080317564Abstract: A wafer supporting device of a sputter apparatus includes a pedestal positioned in a sputtering chamber and used to load a wafer for sputtering, a deposition ring having a recess positioned on a peripheral portion of the pedestal, and a cover ring positioned on the pedestal and the deposition ring. The cover ring has a gate corresponding to the recess.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Inventors: Chi-Piao Cheng, Li-Chun Liang, Yu-Jen Huang, Been Chen
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Patent number: 6658716Abstract: The present invention provides an auxiliary tool for assembling a motor assembly to a wafer-deposition machine for supporting a wafer. The auxiliary tool facilitates easy and quick assembly of the motor assembly to the wafer-deposition machine. An aspect of the present invention is directed to an auxiliary tool for assembling a motor assembly to a wafer-deposition machine, wherein the motor assembly includes a plurality of first screw holes and the wafer-deposition machine includes a plurality of second screw holes corresponding to the first screw holes, respectively. The auxiliary tool comprises a plurality of locking members each having a substantially uniform dimension in a longitudinal direction and being configured to be inserted through one of the plurality of first screw holes of the motor assembly with a corresponding one of the plurality of second screw holes of the wafer-deposition machine to align the first screw hole with the corresponding second screw hole.Type: GrantFiled: March 25, 2002Date of Patent: December 9, 2003Assignee: Mosel Vitelic, Inc.Inventors: Zhi-Zhao Tai, Wen-Kan Hu, Ching-Shun Fan, Li-Chun Liang
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Publication number: 20020148098Abstract: The present invention provides an auxiliary tool for assembling a motor assembly to a wafer-deposition machine for supporting a wafer. The auxiliary tool facilitates easy and quick assembly of the motor assembly to the wafer-deposition machine. An aspect of the present invention is directed to an auxiliary tool for assembling a motor assembly to a wafer-deposition machine, wherein the motor assembly includes a plurality of first screw holes and the wafer-deposition machine includes a plurality of second screw holes corresponding to the first screw holes, respectively. The auxiliary tool comprises a plurality of locking members each having a substantially uniform dimension in a longitudinal direction and being configured to be inserted through one of the plurality of first screw holes of the motor assembly with a corresponding one of the plurality of second screw holes of the wafer-deposition machine to align the first screw hole with the corresponding second screw hole.Type: ApplicationFiled: March 25, 2002Publication date: October 17, 2002Applicant: MOSEL VITELIC, INC.Inventors: Zhi-Zhao Tai, Wen-Kan Hu, Ching-Shun Fan, Li-Chun Liang