Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Abstract: An autonomous mobile robot and an operating method thereof are provided. The autonomous mobile robot includes a movement module, a detection module, a control module and an interaction module. The control module includes a determination unit and a navigation unit. The determination unit determines whether there is an obstacle near or on a predetermined path of the autonomous mobile robot according to the environment information. When the obstacle is on the predetermined path, the navigation unit decides an obstacle avoidance strategy according to the environment information and the type of the obstacle. The obstacle avoidance strategy at least includes moving along a side path, stopping aside to yield, moving backward and stopping at a yielding point to yield, and detouring. When the obstacle is near or on the predetermined path, the interaction module performs an interaction action according to the obstacle avoidance strategy and the type of the obstacle.

Abstract: A caregiving robot and a caregiving system and method employing the same are provided. The caregiving robot includes a movement module, an interaction module and a control module. The interaction module receives an input instruction from the caregiver, and the input instruction includes an identity information and a target location information of the care recipient and a caregiving task information. During execution of the caregiving task, the control module controls the movement module to make the caregiving robot move to a target location according to the target location information. When the caregiving robot arrives at the target location, the control module controls the interaction module to interact with the care recipient according to the caregiving task information so as to collect health status input from the care recipient, and generates a status report accordingly. The status report includes health status information and status evaluation information of the care recipient.

Abstract: A method for manufacturing a semiconductor structure including the following steps is provided. First, a first insulating layer with a conductive contact is formed over a substrate, and a second insulating layer having an opening is formed on the first insulating layer, wherein the opening corresponds to and exposes a top surface of the conductive contact. A conductive line structure is formed in the opening, wherein a contact void is formed between the second insulating layer and the conductive line structure, and then a plasma oxide layer is conformally deposited over the substrate. Then, a wet cleaning process is performed by using an aqueous solution containing negatively charged ions. A capping layer is formed on the plasma oxide layer, the capping layer filling the contact void, and an etching back process to remove the capping layer above the contact void.

Abstract: A method of manufacturing a semiconductor structure includes the following steps. A bit line structure is formed over a substrate. A first spacer layer is formed on a first sidewall of the bit line structure. A second spacer layer is formed on a second sidewall of the first spacer layer. A third spacer layer is formed on a third sidewall of the second spacer layer. An oxidation process is performed on the second spacer layer, thereby forming an oxidized portion and a remaining portion in the second spacer layer, in which the oxidized portion is between the remaining portion and the third spacer layer. A fourth spacer layer is formed on a fourth sidewall of the third spacer layer.

Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A stator structure is provided and includes a plurality of first lamination layers, a plurality of second lamination layers, two third lamination layers and two oil spraying rings. The second lamination layers are sandwiched in between the first lamination layers. The second lamination layer located in the middle of the stator structure is sandwiched in between the two third lamination layers. The two oil spraying rings are connected to two first lamination layers located at outermost sides. Another stator structure is provided and includes a plurality of first lamination layers, a second lamination layer and two oil spraying rings. The second lamination layer is sandwiched in between two first lamination layers. The two oil spraying rings are connected to two first lamination layers located at outermost sides. By means of the arrangement of the aforesaid stator structure, the invention can effectively improve heat dissipating effect for oil cooling.

Abstract: A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. A seal ring within the semiconductor device is extended to include a first bond metal within a bonding layer and bonded to a second bond metal over the semiconductor substrate. Such a seal ring provided a more complete protection from cracking and delamination.

Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: Provided is a method for transmitting signals, including: acquiring a first image by performing a Fourier transform on first data to be transmitted; performing first preprocessing on the first image, wherein the first preprocessing comprises at least one of compression, encryption, or verification; acquiring second data by performing an inverse Fourier transform on the first image after the first preprocessing; and modulating the second data into a first radio frequency signal, and transmitting the first radio frequency signal.

Abstract: A phased array transmitter includes a plurality of signal couplers arranged to receive a radio frequency (RF) input signal, and a plurality of RF transmitters coupled to the signal couplers. Each RF transmitter includes a radiating element, a chip and a phase shifting circuit. The radiating element is arranged to receive a plurality of electrical signals to produce an RF output signal. An amplifier circuit of the chip is configured to amplify the RF input signal to generate a plurality of amplified signals at a plurality of output terminals, respectively. The phase shifting circuit is located outside the chip, and coupled to the output terminals and the radiating element. The phase shifting circuit is arranged to phase shift the amplified signals, and accordingly generate the electrical signals fed to the radiating element. Respective phase shifting circuits and respective radiating elements of the RF transmitters are formed on a same substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Abstract: A method for manufacturing a semiconductor device includes: forming an isolation member defining an active region in a substrate; forming a first insulating layer having a bit line contact over the substrate; forming a second insulating layer having a bit line opening on the first insulating layer; forming a bit line structure in the bit line opening, the bit line structure being electrically connecting to the bit line contact, and a contact void being formed surrounding the bit line structure and exposing a portion of the bit line contact; conformally forming a nitride spacer layer over the bit line structure, the second insulating layer, and the conductive contact; conformally forming a plasma oxide layer over the nitride spacer layer; and performing a wet cleaning process by using an aqueous solution containing negatively charged ions.

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Abstract: A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.

Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.