Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Abstract: An antenna package is provided. The antenna package includes a glass substrate, a plurality of antennas, a multi-layer circuit structure, and a plurality of radio frequency chips. The glass substrate has a first surface and a second surface. The plurality of antennas are arranged on the first surface of the glass substrate. The multi-layer circuit structure has a first surface and a second surface. The plurality of radio frequency chips are arranged on the first surface of the multi-layer circuit structure. The second surface of the glass substrate is adhered to the second surface of the multi-layer circuit structure.

Abstract: A method of forming a semiconductor structure includes forming a conductive structure in a first dielectric layer. A second dielectric layer is formed over the first dielectric layer. A conductive contact is formed in the second dielectric layer. The second dielectric layer is etched to form a recess on a top surface of the conductive structure. A native oxide layer is formed on a top surface and a sidewall of the second dielectric layer, the top surface of the conductive structure, and a sidewall of the conductive contact. A first plasma process is performed to form a first material layer over the native oxide layer by using a first plasma gas. A second plasma process is performed to form a second material layer over the first material layer by a second plasma gas different from the first plasma gas. A spacer layer is formed on the second material layer.

Abstract: Disclosed is a satellite communication handover method, which includes: determining a scene where a user equipment is located according to a measurement report of the user equipment, determining a handover parameter corresponding to the scene, and sending a handover command is sent to the user equipment to instruct the user equipment to perform handover when the user equipment satisfies a first handover condition which is based on the handover parameter.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: A three-dimensional printing apparatus includes a liquid tank capable of accommodating a photosensitive liquid. The liquid tank includes a film, a plurality of side walls, a plate and a motor. The film has a workpiece curing area. The plurality of side walls surrounds the film. The plate is capable of supporting the film and having at least one fluid tunnel extending from a first surface of the plate contacting the film to a second surface of the plate. The motor is connected to the liquid tank to incline the liquid tank. A gap is formed between the plat and one of the plurality of side walls of the liquid tank, and the film is communicated with an outside space via the gap.

Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Abstract: A method of testing an antenna array includes: receiving a probe needle set and a shielding structure, wherein the shielding structure includes an array of conductive pads. The antenna array includes a substrate and an array of antenna devices. Each of the antenna devices includes: a first and a second slits; a first and a second signal ports; a first and a second feed lines. The first and second feed lines have different line lengths; and a radiation element. The method further includes: causing the shielding structure to cover the radiation element of at least one antenna device; and causing the probe needle set to contact the first and second feed lines for testing the at least one antenna device.

Abstract: A wireless communication system includes a plurality of antennas, and a plurality of RF chips, arranged in a row and coupled to the antennas, for providing a plurality radio-frequency (RF) output signals to the antennas according to an RF signal. The wireless communication system also includes a transmission line arranged to be a straight line in parallel to the row, and to connect to the RF chips, and a resistive load, coupled to a first end of the transmission line. A second end of the transmission line is arranged to receive the RF signal.

Abstract: An antenna device includes: a substrate; a first ground plate arranged in a first layer and disposed on the substrate; a first signal port and a second signal port arranged in a second layer adjacent to the first layer and configured to transmit a first radio-frequency (RF) signal and a second RF signal, respectively; a first feed line and a second feed line arranged in the second layer and connected to the first signal port and the second signal port, respectively; and a radiation element disposed over the substrate. The substrate is arranged to provide a first signal channel and a second signal channel between the radiation element and the first or second feed line for transmitting the first and second RF signals, the first feed line and the second feed line have different line lengths, and the radiation element at least partially overlaps the first and second signal channels.

Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.

Abstract: An antenna package structure is provided. The antenna package structure includes a glass substrate, an interconnect structure, a plurality of semiconductor chips, and an antenna array structure. The glass substrate has a first surface and a second surface opposite to the first surface. The interconnect structure is disposed over the first surface of the glass substrate. The plurality of semiconductor chips are mounted over the interconnect structure. The antenna array structure is formed on the second surface of the glass substrate. Furthermore, the plurality of semiconductor chips are coupled to the antenna array structure through the interconnect structure and the glass substrate.

Abstract: The present disclosure relates to a system, a method and a computer-readable medium for quality prediction. The method includes obtaining values of a parameter of a first endpoint, obtaining values of a parameter of a second endpoint, and generating a prediction of the parameter of the first endpoint according to the values of the parameter of the first endpoint and the values of the parameter of the second endpoint. The prediction includes probability distribution information of the parameter of the first endpoint at a timing in the future. The present disclosure can result in a more precise quality prediction.

Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.

Abstract: A method for manufacturing a semiconductor structure is provided. First, a first insulating layer is formed over a substrate, and a second insulating layer having an opening is formed over the first insulating layer. A conductive line structure is formed in the opening of the second insulating layer, thereby forming a contact void between the second insulating layer and the conductive line structure. A plasma oxide layer is conformally formed over the conductive line structure, the first insulating layer, and the contact void. A nitride capping layer is formed over the plasma oxide layer to fill the contact void. Then, nitrogen ions are introduced into a surface of the nitride capping layer surrounding the conductive line structure. An etching back process is performed to remove a portion of the nitride capping layer, thereby forming a refilled contact void between the first insulating layer and the conductive line structure.

Abstract: A method for manufacturing a semiconductor device includes: forming an isolation member defining an active region in a substrate; forming a first insulating layer having a bit line contact over the substrate; forming a second insulating layer having a bit line opening on the first insulating layer; forming a bit line structure in the bit line opening, the bit line structure being electrically connecting to the bit line contact, and a contact void being formed surrounding the bit line structure and exposing a portion of the bit line contact; conformally forming a nitride spacer layer over the bit line structure, the second insulating layer, and the conductive contact; conformally forming a plasma oxide layer over the nitride spacer layer; and performing a wet cleaning process by using an aqueous solution containing negatively charged ions.