Patents by Inventor Li-Hsuan Yeh
Li-Hsuan Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240071849Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
-
Patent number: 11626398Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.Type: GrantFiled: March 11, 2021Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ta-Wei Lin, Fu-Hsiung Yang, Ching-Hsun Hsu, Yu-Lun Lu, Li-Hsuan Yeh, Tsung-Chieh Tsai, Kong-Beng Thei
-
Publication number: 20220293590Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Inventors: TA-WEI LIN, FU-HSIUNG YANG, CHING-HSUN HSU, YU-LUN LU, LI-HSUAN YEH, TSUNG-CHIEH TSAI, KONG-BENG THEI
-
Publication number: 20210280577Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: ApplicationFiled: May 10, 2021Publication date: September 9, 2021Inventors: Yi-Huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
-
Patent number: 11004844Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: GrantFiled: July 25, 2018Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
-
Patent number: 10916542Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: GrantFiled: March 4, 2016Date of Patent: February 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
-
Patent number: 10325964Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.Type: GrantFiled: November 15, 2016Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Fu-Jier Fan, Kong-Beng Thei, Ker-Hsiao Huo, Li-Hsuan Yeh, Yu-Bin Zhao
-
Patent number: 10164037Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.Type: GrantFiled: March 31, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ker-Hsiao Huo, Kong-Beng Thei, Chih-Wen Albert Yao, Fu-Jier Fan, Chen-Liang Chu, Ta-Yuan Kung, Yi-Huan Chen, Yu-Bin Zhao, Ming-Ta Lei, Li-Hsuan Yeh
-
Publication number: 20180350801Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: ApplicationFiled: July 25, 2018Publication date: December 6, 2018Inventors: Yi-huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen
-
Publication number: 20180286960Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Ker-Hsiao HUO, Kong-Beng THEI, Chih-Wen Albert YAO, Fu-Jier FAN, Chen-Liang CHU, Ta-Yuan KUNG, Yi-Huan CHEN, Yu-Bin ZHAO, Ming-Ta LEI, Li-Hsuan YEH
-
Publication number: 20180138250Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventors: Yi-Huan Chen, Fu-Jier Fan, Kong-Beng Thei, Ker-Hsiao Huo, Li-Hsuan Yeh, Yu-Bin Zhao
-
Publication number: 20170194320Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.Type: ApplicationFiled: March 4, 2016Publication date: July 6, 2017Inventors: Yi-huan Chen, Kong-Beng Thei, Fu-Jier Fan, Ker-Hsiao Huo, Kau-Chu Lin, Li-Hsuan Yeh, Szu-Hsien Liu, Yi-Sheng Chen