Patents by Inventor Li Lin
Li Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12387033Abstract: An information insertion method performed by a computer device relates to the field of information processing. The method includes: displaying an editing interface corresponding to an online document; receiving a contact insertion operation in the editing interface; in response to the contact insertion operation, inserting a contact corresponding to a first account into the online document; and displaying the contact corresponding to the first account in the online document, the contact corresponding to the first account providing a communication portal for instant messaging with the first account through the online document.Type: GrantFiled: June 30, 2023Date of Patent: August 12, 2025Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Tieming Huang, Yang Zhou, Rui Tang, Li Lin, Bin Li
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Patent number: 12379462Abstract: A height measurement device and a height measurement method based on a millimeter-wave radar are provided. The height measurement device comprises a millimeter-wave radar module, a main controller, and a wake-up module. The wake-up module and the millimeter-wave radar module are connected to the main controller, respectively. The wake-up module activates the millimeter-wave radar module through the main controller. The millimeter-wave radar module sends a transmission signal and receives an echo signal, and obtains an intermediate-frequency signal based on the transmission signal and the echo signal. The echo signal is formed by the reflected back transmission signal after it encounters human head. The main controller applies continuous millimeter waves to sweep across the highest point of the human head and obtain height data based on the intermediate-frequency signal.Type: GrantFiled: November 1, 2024Date of Patent: August 5, 2025Assignee: Airtouch Intelligent Technology (Shanghai) Co., Ltd.Inventors: Shuiyang Lin, Huaping Wu, Li Lin, Yantao Guo, Zhilin Wang
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Publication number: 20250241306Abstract: Present invention teaches the method of using a keratin hydrolysis peptide (“KHP”) solution to prevent cabbage black spot disease caused by the pathogen of Alternaria brassicicola. By selectively choosing specific weights of feathers and water, and treating the mixture to a high-temperature high-pressure hydrolysis process, the resulting solution is confirmed to contain at least 253 peptides and then apply to the cabbage plants by infusing to the soil containing the cabbage plants. Optionally, the KHP solution can be diluted by water, as disclosed in the specification before infusing to the soil.Type: ApplicationFiled: July 19, 2024Publication date: July 31, 2025Applicant: CH Biotech R&D Co., Ltd.Inventors: Yi-Ting YEH, Chiu-Li LIN, Jenn Wen HUANG, Jie-Chao YOU, Huan-Hsuan LIANG, Nai-Hua YE
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Patent number: 12369155Abstract: Various solutions for scheduling restriction with higher subcarrier spacing (SCS) with respect to user equipment and network apparatus in mobile communications are described. An apparatus may determine whether a capability is enabled. The apparatus may apply a scheduling restriction on K symbols before synchronization signal block (SSB) symbols and K symbols after the SSB symbols in an event that the capability is enabled. The K symbols are greater than 1 symbol. The apparatus may transmit uplink symbols or receiving downlink symbols outside the symbols with the scheduling restriction.Type: GrantFiled: September 14, 2022Date of Patent: July 22, 2025Assignee: MediaTek Inc.Inventor: Hsuan-Li Lin
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Publication number: 20250234592Abstract: Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure from a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked, removing edge portion of the second semiconductor layers by an etch process, after the etch process, subjecting the second semiconductor layers to a post-treatment process to remove residues from exposed surfaces of the second semiconductor layers. The method also includes after the post-treatment process, subjecting the treated surfaces of the second semiconductor layers to a pre-clean process. The method further includes forming an inner spacer in contact with the treated surfaces of the second semiconductor layers.Type: ApplicationFiled: January 15, 2024Publication date: July 17, 2025Inventors: Bo Wei LAN, Chih-Teng LIAO, Yu-Li LIN, Ya-Wei LIAO
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Patent number: 12358101Abstract: The present disclosure relates to the technical field of automobile part processing, and specifically provides a clamping device and a sandblasting device for automobile part processing. The clamping device comprises a clamping component for clamping an automobile part, and an auxiliary component; the auxiliary component comprises a supporting part, a pull rod, a protective pad, and a return spring, wherein the pull rod is movably provided on the supporting part, one end of the pull rod is connected to the protective pad having deformation performance, and the protective pad is used for being arranged between the automobile part and the clamping component; the return spring is used for being installed between the supporting part and the protective pad; the pull rod is pulled so that the pull rod pulls the protective pad to move towards the direction close to the supporting part.Type: GrantFiled: October 20, 2022Date of Patent: July 15, 2025Assignee: Zhejiang Wanli UniversityInventors: Jingwei Ning, Xiang Yan, Wen Liu, Hongwei Cui, Hang Wang, Chi Zhang, Li Lin, Peichao Wang, Yeying Teng
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Patent number: 12360543Abstract: A reference voltage generator circuit includes: a first transistor and a second transistor, wherein the first transistor and the second transistor are coupled with each other and are located on a substrate, wherein the first transistor has a first conduction threshold voltage and a first rated voltage, wherein the second transistor has a second conduction threshold voltage and a second rated voltage, wherein the first rated voltage is higher than the second rated voltage; wherein the reference voltage generator circuit is configured to generate a bandgap reference voltage with temperature compensation according to a difference between the first conduction threshold voltage and the second conduction threshold voltage.Type: GrantFiled: October 17, 2023Date of Patent: July 15, 2025Assignee: Richtek Technology CorporationInventors: Chien-Yu Chen, Li Lin, Cheng-Kuang Lin, Yue-Hung Tang, Ting-Wei Liao, Shao-Hung Lu
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Publication number: 20250216056Abstract: A light adjustment device and an illumination device are disclosed. The light adjustment device includes a base, a piezoelectric component, and a flexible reflective sheet. The base is for disposing a light emission device thereon. The piezoelectric component is mounted on the base and generates a deformation amount with a preset value toward a preset direction by changing the voltage inputted to the piezoelectric component. One side of the flexible reflective sheet is fixed on the piezoelectric component. The flexible reflective sheet generates a preset bend to form a reflective curved surface by the deformation of the piezoelectric component, and the light emitted by the light emission device partially projects or entirely projects onto the reflective curved surface of the flexible reflective sheet and is reflected on a preset position.Type: ApplicationFiled: May 24, 2024Publication date: July 3, 2025Inventors: Hsi-Sheng HSIA, Jhih-Li LIN
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Publication number: 20250216463Abstract: The present invention provides a battery quality detection method, comprising the following steps: selecting a plurality of test data with a data concentration greater than a first threshold; determining an upper limit curve and a lower limit curve for the selected test data; setting a standard detection range between the upper limit curve and the lower limit curve; obtaining a battery characteristic waveform of a battery; and comparing the battery characteristic waveform with the standard detection range to evaluate the battery's quality.Type: ApplicationFiled: December 23, 2024Publication date: July 3, 2025Inventors: Jih-Hsing LEE, Chia-Li LIN, Hui-Shan LIU
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Publication number: 20250209844Abstract: Provided are a method and a device for recognizing an ancient book. The method comprises: extracting classification features of a target ancient book image based on a backbone network to obtain backbone classification features; detecting the backbone classification features and determining individual character positions and text line positions included in the target ancient book image; recognizing the individual character positions to obtain content information of individual characters, and predicting the text line positions to obtain a reading order of characters in the text line positions; and arranging, based on a ratio between the individual character positions and the text line positions, the content information of the individual characters following the reading order of the characters in the text line positions to obtain a recognition result of characters in the target ancient book image.Type: ApplicationFiled: February 2, 2023Publication date: June 26, 2025Inventors: Yuxuan ZHANG, Li LIN, Can HUANG, Changhu WANG
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Patent number: 12334003Abstract: A pixel circuit is provided. A reader reads a first data voltage and a threshold voltage of a target compensation transistor on a current path of a driving current in a light-emitting driver to a control terminal of the target compensation transistor during a read period. During a light-emitting period, the reader uses a second data voltage to compensate the control terminal of the target compensation transistor, which ensures that the driving current is only related to the first data voltage. The second data voltage is twice voltage value of the first data voltage.Type: GrantFiled: June 19, 2024Date of Patent: June 17, 2025Assignee: AUO CorporationInventor: Wei-Li Lin
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Publication number: 20250191526Abstract: A light-emitting signal generating circuit includes a first transistor, having a first terminal for receiving a first light-emitting signal, a gate terminal for receiving a first clock signal, and a second terminal that generates a control signal; a second transistor that has a first terminal for receiving a first reference voltage, a gate terminal, and a second terminal for outputting a second light-emitting signal; a first capacitor having a first terminal for receiving a second clock signal, and a second terminal coupled to the second terminal of the first transistor and a gate terminal of the second transistor, wherein a low level period of the first clock signal partially overlaps with a low level period of the second clock signal, and a falling edge of the second clock signal lags behind a falling edge of the first clock signal.Type: ApplicationFiled: October 9, 2024Publication date: June 12, 2025Inventors: Wei-Li LIN, Yen-Wei Yeh
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Publication number: 20250191875Abstract: A vacuum chamber system comprises a supporting structure configured to support an object to be thermally stabilized, a plate, having a first surface facing the object, positioned such that the first surface is located within a predetermined distance from the object when the object is placed on the supporting structure, the plate being thermally coupled to a heat conduction source, and a chamber enclosing the supporting structure and the plate.Type: ApplicationFiled: February 10, 2023Publication date: June 12, 2025Applicant: ASML Netherlands B.V.Inventors: Dongchi YU, Jun-li LIN, Shao-Wei FU, Yi-Chen LIN, Hongbo FAN
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Publication number: 20250194200Abstract: A dummy gate structure may be formed for a semiconductor device. The dummy gate structure may be formed from an amorphous polysilicon layer. The amorphous polysilicon layer may be deposited in a blanket deposition operation. An annealing operation is performed for the semiconductor device to remove voids, seams, and/or other defects from the amorphous polysilicon layer. The annealing operation may cause the amorphous polysilicon layer to crystallize, thereby resulting in the amorphous polysilicon layer transitioning into a crystallized polysilicon layer. A dual radio frequency (RF) source etch technique may be performed to increase the directionality of ions and radicals in a plasma that is used to etch the crystallized polysilicon layer to form the dummy gate structure. The increased directionality of the ions increases the effectiveness of the ions in etching through the different crystal grain boundaries which increases the etch rate uniformity across the crystallized polysilicon layer.Type: ApplicationFiled: January 28, 2025Publication date: June 12, 2025Inventors: Yan-Ting SHEN, Yu-Li LIN, Jui Fu HSIEH, Chih-Teng LIAO
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Publication number: 20250179135Abstract: A keratinocyte growth factor (KGF)-transdermal peptide (TP) fusion protein is provided. The amino acid sequence of the KGF-TP fusion protein is shown as SEQ ID NO: 12. The nucleotide sequence of a gene encoding the KGF-TP fusion protein is shown as SEQ ID NO: 8. A recombinant pGM3301 vector containing the gene is also provided. A preparation method and application of the KGF-TP fusion protein are also provided.Type: ApplicationFiled: January 17, 2025Publication date: June 5, 2025Inventors: Xiaokun LI, Li LIN, Shuang GAO, Fanghua GONG, Lishang DAI, Zhenlin HU, Haitao XI, Jisheng MA, Yunpeng WANG, Nuo XU
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Publication number: 20250175073Abstract: A power conversion and transmission system includes a power provider unit, a load unit and a cable. The power provider unit includes a power conversion circuit for converting an input power into an intermediate power, and a path switch coupled between the intermediate power and a bus power. The cable includes a power sub-cable, a communication sub-cable, and a ground sub-cable, for coupling the provider-end power, communication, and ground nodes of the power provider unit respectively to the corresponding nodes of the load unit. At an initial time point, voltage the of the provider-end communication node is sensed and recorded as the initial voltage level. At a determination time point, if the difference between the present voltage level of the provider-end communication node and the initial voltage level exceeds a threshold value, a power source limiting operation is initiated.Type: ApplicationFiled: November 7, 2024Publication date: May 29, 2025Inventors: Shin-Li Lin, Kun-Han Yang, Syuan-Zong Lan, Ta-Yung Yang
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Patent number: 12315434Abstract: A display includes a first light emitting device. The first light emitting device includes a first switch and a second switch. The first switch is configured to adjust a first node according to a first clock signal. The second switch is configured to generate a first light emitting signal according to a first voltage signal. A control end of the second switch is coupled to the first node. The first clock signal switches between a first voltage level and a second voltage level. The first voltage signal has a third voltage level. The third voltage level is more than one of the first voltage level and the second voltage level and is less than the other one of the first voltage level and the second voltage level.Type: GrantFiled: December 27, 2023Date of Patent: May 27, 2025Assignee: AUO CORPORATIONInventors: Che-Wei Tung, Wei-Li Lin, Chin-Hao Chang, Wei-Kai Huang
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Patent number: 12315864Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.Type: GrantFiled: August 9, 2023Date of Patent: May 27, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Chi Yu, Jui Fu Hsieh, Yu-Li Lin, Chih-Teng Liao, Yi-Jen Chen
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Patent number: 12300644Abstract: In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.Type: GrantFiled: June 15, 2022Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Chia-Li Lin, Yu-Chih Huang, Chen-Shien Chen
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Publication number: 20250150371Abstract: In various examples, latency of human interface devices (HIDs) may be accounted for in determining an end-to-end latency of a system. For example, when an input is received at an HID, an amount of time for the input to reach a connected device may be computed by the HID and included in a data packet transmitted by the HID device to the connected device. The addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an HID is determined to have a non-negligible contribution to the end-to-end latency, a new HID component may be implemented, a configuration setting associated with the HID component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.Type: ApplicationFiled: January 10, 2025Publication date: May 8, 2025Inventors: David Lim, Hsien-Li Lin, Tom Jozef Denis Verbeure, Gerrit Slavenburg, Seth Schneider