Patents by Inventor Li-Lin Su
Li-Lin Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240339406Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.Type: ApplicationFiled: June 21, 2024Publication date: October 10, 2024Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
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Patent number: 12062611Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.Type: GrantFiled: February 7, 2022Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
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Publication number: 20240085803Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Patent number: 11860550Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: GrantFiled: July 19, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Publication number: 20220350262Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I YANG, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Patent number: 11422475Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: GrantFiled: December 20, 2019Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Publication number: 20220157720Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
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Patent number: 11251131Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.Type: GrantFiled: June 17, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
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Patent number: 11244898Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.Type: GrantFiled: April 10, 2019Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
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Patent number: 11127680Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: GrantFiled: June 23, 2017Date of Patent: September 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee, Shau-Lin Shue
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Patent number: 11088020Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.Type: GrantFiled: August 30, 2017Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Li-Lin Su, Shin-Yi Yang, Cheng-Chi Chuang, Hsin-Ping Chen
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Publication number: 20200321279Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.Type: ApplicationFiled: June 17, 2020Publication date: October 8, 2020Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
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Patent number: 10700010Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.Type: GrantFiled: April 3, 2017Date of Patent: June 30, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
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Publication number: 20200124985Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Patent number: 10534273Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: GrantFiled: May 4, 2017Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
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Publication number: 20200006228Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.Type: ApplicationFiled: April 10, 2019Publication date: January 2, 2020Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
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Publication number: 20190067089Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-I YANG, Wei-Chen CHU, Li-Lin SU, Shin-Yi YANG, Cheng-Chi CHUANG, Hsin-Ping CHEN
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Publication number: 20180164698Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.Type: ApplicationFiled: May 4, 2017Publication date: June 14, 2018Inventors: Tai-I YANG, Wei-Chen CHU, Hsiang-Wei LIU, Shau-Lin SHUE, Li-Lin SU, Yung-Hsu WU
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Patent number: 9935006Abstract: The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.Type: GrantFiled: March 2, 2017Date of Patent: April 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Chang Wu, Li-Lin Su
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Publication number: 20170287842Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.Type: ApplicationFiled: June 23, 2017Publication date: October 5, 2017Inventors: Shih-Kang FU, Hsien-Chang WU, Li-Lin SU, Ming-Han LEE, Shau-Lin SHUE