Patents by Inventor Li-Lin Su

Li-Lin Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385540
    Abstract: An exposure tool is configured to remove contaminants and/or prevent contamination of mirrors and/or other optical components included in the exposure tool. In some implementations, the exposure tool is configured to flush and/or otherwise remove contaminants from an illuminator, a projection optics box, and/or one or more other subsystems of the exposure tool using a heated gas such as ozone (O3) or extra clean dry air (XCDA), among other examples. In some implementations, the exposure tool is configured to provide a gas curtain (or gas wall) that includes hydrogen (H2) or another type of gas to reduce the likelihood of contaminants reaching the mirrors included in the exposure tool. In this way, the mirrors and one or more other components of the exposure tool are cleaned and maintained in a clean environment in which radiation absorbing contaminants are controlled to increase the performance of the exposure tool.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Kai-Chieh CHANG, Che-Chang HSU, Yen-Shuo SU, Chun-Lin CHANG, Kai-Fa HO, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20240379454
    Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Hui-Lin Huang, Li-Li Su, Yee-Chia Yeo, Chii-Horng Li
  • Publication number: 20240369938
    Abstract: An extreme ultra violet (EUV) lithography method includes receiving an EUV light by a scanner from an EUV light source, the EUV light passing through an intermediate focus disposed in the scanner and at a junction of the EUV light source and the scanner; directing the EUV light by the scanner to a reticle in the scanner; and deflecting nanoparticles from the EUV light source away from the reticle by generating a gas flow using a gas jet disposed entirely in the scanner and proximate to an interface of the scanner and the intermediate focus such that the gas jet does not block the EUV light.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ping YEN, Yen-Shuo SU, Chieh HSIEH, Shang-Chieh CHIEN, Chun-Lin CHANG, Li-Jui CHEN, Heng-Hsin LIU
  • Patent number: 12130555
    Abstract: An extreme ultra violet (EUV) lithography method includes receiving an EUV light by a scanner from an EUV light source, the EUV light passing through an intermediate focus disposed in the scanner and at a junction of the EUV light source and the scanner; directing the EUV light by the scanner to a reticle in the scanner; and deflecting nanoparticles from the EUV light source away from the reticle by generating a gas flow using a gas jet disposed entirely in the scanner and proximate to an interface of the scanner and the intermediate focus such that the gas jet does not block the EUV light.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ping Yen, Yen-Shuo Su, Chieh Hsieh, Shang-Chieh Chien, Chun-Lin Chang, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 12124854
    Abstract: A computer program product embodied on a non-transitory computer readable medium of a control system includes a firmware program file, a signature detection module that causes a processor to detect whether a pre-defined signature is present; a booting module that causes the processor to perform, after it is determined that the pre-defined signature is not present in the main block, operations of power management and pin initiation included in the booting sequence; and a flashing module that causes the processor to perform, in response to receipt of a flashing command, a flashing operation that includes overwriting the firmware program file with an update firmware program file.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: October 22, 2024
    Assignee: FLYTECH TECHNOLOGY CO., LTD.
    Inventors: Li-Chun Chou, Shui-Chin Tsai, Ting-You Liou, Chien-Lin Su
  • Publication number: 20240339406
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 10, 2024
    Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
  • Patent number: 12114412
    Abstract: A method for monitoring a shock wave in an extreme ultraviolet light source includes irradiating a target droplet in the extreme ultraviolet light source apparatus of an extreme ultraviolet lithography tool with ionizing radiation to generate a plasma and to detect a shock wave generated by the plasma. One or more operating parameters of the extreme ultraviolet light source is adjusted based on the detected shock wave.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Shuo Su, Jen-Hao Yeh, Jhan-Hong Yeh, Ting-Ya Cheng, Henry Yee Shian Tong, Chun-Lin Chang, Han-Lung Chang, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 12062611
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
  • Publication number: 20240258429
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Patent number: 12051896
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Publication number: 20240085803
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11860550
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Publication number: 20220350262
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I YANG, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11422475
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Publication number: 20220157720
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
  • Patent number: 11251131
    Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
  • Patent number: 11244898
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: February 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tai-I Yang, Li-Lin Su, Yung-Hsu Wu, Hsin-Ping Chen, Cheng-Chi Chuang
  • Patent number: 11127680
    Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11088020
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Li-Lin Su, Shin-Yi Yang, Cheng-Chi Chuang, Hsin-Ping Chen
  • Publication number: 20200321279
    Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau