Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, strained layers, source/drain contact patterns, a gate contact via, and source/drain contact vias. The gate structure is disposed over the semiconductor substrate. The strained layers are disposed aside the gate structure. The source/drain contact patterns are disposed on and electrically connected to the strained layers. Top surfaces of the source/drain contact patterns are coplanar with a top surface of the gate structure. The gate contact via is disposed on and electrically connected to the gate structure. The source/drain contact vias are disposed on and electrically connected to the source/drain contact patterns.

Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.

Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

Abstract: A microscope system (100) configured to record images in at least a first and a second imaging mode (501, 502), comprising: An objective (1) collecting light (201) from a sample (11), An illumination module coupled to the objective, A first reimaging objective (5) generating an intermediate image of the sample and a second reimaging objective (6) that relays the intermediate image onto a detection module, An evaluation module (200) comprising a machine learning method (DL), trained with a first and a second set of images of the same sample, wherein the first and second set has been acquired in the first (501) and second imaging mode (502), respectively, wherein upon acquisition of an image (400) in the second imaging mode (502) the trained machine learning method (DL) outputs a restored image (401) that comprises fewer aberrations than the image (400) acquired in the second imaging mode (52, 53, 57).

Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.

Abstract: A light-emitting module of an illuminated keyboard includes a reflector plate, a light guiding plate, a light shielding plate, a base plate, a thin film circuit board, and a light-emitting element. The light guiding plate is disposed on the reflector plate. The light shielding plate is disposed on the light guiding plate and includes a through hole and a first light-passing hole that is spaced apart from the through hole. The base plate is disposed on the light shielding plate and includes an accommodating hole that is aligned with the through hole and a second light-passing hole that is spaced part from the accommodating hole and that is aligned with the first light-passing hole. The thin film circuit board is disposed on the base plate. The light-emitting element is disposed on the thin film circuit board and extends into the accommodating hole.

Abstract: A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar.

Abstract: A package structure is provided. The package structure includes a redistribution structure on a substrate, a semiconductor die on the redistribution structure and electrically connected to the substrate, a wall structure on the redistribution structure and electrically isolated from the substrate. The semiconductor die includes a first sidewall, a second sidewall connected to the first sidewall, and a third sidewall connected to the second sidewall. The wall structure includes a first partition, a second partition and a third partition respectively immediately adjacent to the first sidewall, the second sidewall, and the third sidewall of the semiconductor die. The first partition is located immediately adjacent to and spaced apart from the second partition by a first distance, the second partition is located immediately adjacent to and spaced apart from the third partition by a second distance, and the first distance is substantially equal to the second distance.

Abstract: A furandicarboxylate polymer has a character index that ranges from 0.27 to 0.55 and that is calculated using the following Equation: Character index=[(AC1×Mn1÷(2×106)], where AC1 represents an acid value of the furandicarboxylate polymer, and Mn1 represents a number average molecular weight of the furandicarboxylate polymer.

Abstract: A heat-shrinkable polyester film includes a polyester resin made from a dicarboxylic component including at least one of terephthalic acid and dimethyl terephthalate, and a diol component including ethylene glycol, 2-methyl-1,3-propanediol, and a diol selected from neopentyl glycol, 1,4-cyclohexanedimethanol, and a combination thereof. Based on 100 mol % of the diol component, the ethylene glycol, the diol mixture and the 2-methyl-1,3-propanediol are present in amounts ranging from 74 mol % to 82 mol %, from 18 mol % to 26 mol %, and from 3.5 mol % to 22 mol %, respectively. The heat-shrinkable polyester film has, after immersion in hot water at 95° C. for 10 seconds, a heat shrinkage in a direction transverse to a machine direction (TD) of greater than 48%, a heat shrinkage in the machine direction of less than 5%, an intrinsic viscosity of greater than 0.5 dL/g, and a yield strength in the TD ranging from 7.5 MPa to 13 MPa.

Abstract: A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring. The package structure also includes a substrate on a second surface of the redistribution structure through third bonding elements and in electrical connection with the semiconductor die.

Abstract: A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.

Abstract: A semiconductor structure includes a base structure including a substrate and a device unit disposed on a front surface of the substrate, a front dielectric portion disposed on the front surface to cover the device unit, a front conductive layer disposed in the front dielectric portion and connected to the device unit, a back dielectric unit disposed on a back surface of the substrate opposite to the front surface and including at least one first part which includes a first dielectric portion having a thermal conductivity which is greater than that of the front dielectric portion, and a back conductive unit which is disposed in the back dielectric unit and connected to the device unit, and which includes at least one first conductive layer disposed in the at least one first part.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure having a dielectric structure and multiple wiring layers in or over the dielectric structure and a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure also includes a first chip structure bonded to the redistribution structure and electrically insulated from the shield bump structure, and the first chip structure has a first sidewall. The chip package structure further includes a second chip structure bonded to the redistribution structure and electrically insulated from the shield bump structure. The first chip structure and the second chip structure are spaced apart from each other by a gap, and the shield bump structure extends across the gap. The first sidewall faces away from the second chip structure, and the shield bump structure extends across the first sidewall.

Abstract: A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.

Abstract: A light emitting module includes a light-guiding plate disposed under a light-shielding plate that includes a light-shielding portion and a hollow unit. The light-guiding plate has a light-exiting surface, a bottom surface, and a light-entering surface unit. The light-exiting surface has a base portion and a light-mixing portion. The light-mixing portion is formed on the base portion, is disposed within the hollow unit, and has refracting segments. Each of the refracting segments extends and tapers upwardly from the base portion. A reflection plate is disposed under the bottom surface. A plurality of light emitting members are disposed below the light-shielding portion. The light-entering surface unit faces the light emitting members.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: The present invention provides an FFR determination method and apparatus based on multi-modal medical image, a device, and a medium. The method includes: obtaining an intravascular image comprising a blood vessel segment of interest; obtaining an extravascular image comprising a blood vessel segment to be detected, where the blood vessel segment to be detected at least partially coincides with the blood vessel segment of interest; performing registration on the intravascular image and the extravascular image to obtain a registration result; and determining a target fractional flow reserve based on multi-modal medical image by using the registration result on the basis of the intravascular image and the extravascular image.

Abstract: A package structure is provided. The package structure includes a package component over a redistribution structure, a substrate under the redistribution structure, and an underfill material over the redistribution structure and including a first extending portion in the structure. The package component has a first sidewall and a second sidewall connected to the first sidewall at a first corner. In a plan view, the first extending portion has a first sidewall passing through the first sidewall of the package component and a second sidewall opposite to the first sidewall of the first extending portion and passing through the second sidewall of the package component.