Abstract: Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The redistribution structure includes a first redistribution structure portion physically and electrically connected to the first semiconductor die, a second redistribution structure portion physically and electrically connected to the second semiconductor die, and a dummy bump region positioned between and electrically isolated from the first redistribution structure portion and the second redistribution structure portion.

Abstract: A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer. The die is electrically bonded to the interposer and disposed over the interconnection structure. The conductive terminal is connected to the interposer and the die via a conductive bump. In order to effectively avoid cold joint issues, round or rectangular polyimide structures are first disposed under the bumps to structurally support the bump and sufficiently increase bump height for improved electrical connection and long term reliability of the package structure.

Abstract: Semiconductor packages and methods of fabricating semiconductor packages include bonding structures on a surface of an interposer having non-uniform height dimensions in different regions of the interposer. A plurality of solder connections may contact the pillars and electrically connect the respective pillars of the interposer to corresponding bonding structures on a package substrate. The variation in the heights of the pillars in different regions of the interposer may compensate for warping of the interposer and improve the reliability of the electrical connections between the interposer and the package substrate.

Abstract: Some implementations herein describe a semiconductor package. The semiconductor package, which may correspond to a high-performance computing semiconductor package, includes an interposer. The interposer includes tapered interconnect structures formed using a laser plug process. The tapered interconnect structures may include a length that is lesser relative to a length of the column-shaped interconnect structures formed using a through-silicon via process. Such a length reduces a thickness of the interposer and reduces a length of electrical connections through the interposer. In this way, a signal integrity may be increased and parasitics of the semiconductor package including the tapered interconnect structures may be reduced to increase a performance of the semiconductor package. Additionally, the reduced thickness of the interposer may reduce an overall thickness of the semiconductor package to save space consumed by the semiconductor package in a computing system.

Abstract: A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure including fan-out bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure; a packaging substrate comprising chip-side bonding pads; an array of solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads; a second underfill material portion laterally surrounding the array of solder material portions; and at least one buffer block structure located between a respective neighboring pair of solder material portions within the array of solder material portions and between the fan-out package and the packaging substrate, and laterally surrounded by the second underfill material portion.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.

Abstract: A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring.

Abstract: Devices and method for forming a chip package structure including at least one semiconductor die attached to a redistribution structure, a molding compound die frame laterally surrounding the at least one semiconductor die, and a first underfill material portion located between the redistribution structure and the at least one semiconductor die and contacting sidewalls of the at least one semiconductor die and sidewalls of the molding compound die frame. The first underfill material portion may include at least one cut region, in which the first underfill material portion may include a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Abstract: A semiconductor structure and methods for forming the same including a package comprising at least one semiconductor die, a redistribution structure comprising bonding pads, and a first underfill material portion located between the at least one semiconductor die and the redistribution structure, a substrate package comprising chip-side bonding pads and at least one substrate trench, in which the at least one substrate trench extends vertically below a top surface of the substrate package in a cross-section view, solder material portions bonded to the chip-side bonding pads and the bonding pads, and a second underfill material portion laterally surrounding the solder material portions and dispensed within the at least one substrate trench.

Abstract: The invention relates generally to the field of wound healing. In one embodiment is a method for generating a delayed wound model in an animal, the method comprising contacting a wound with a composition comprising an electrospun scaffold, wherein the scaffold is made from 80% PCL and 20% rat tail collagen and has been soaked in a biofilm conditioned media from Staphylococcus aureus or a small molecular drug FK866.

Abstract: A method for forming a chip package structure is provided. The method includes forming a dielectric layer over a redistribution structure. The redistribution structure includes a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The method includes forming a first conductive bump structure and a shield bump structure over the dielectric layer. The first conductive bump structure is electrically connected to the wiring layers, and the shield bump structure is electrically insulated from the wiring layers. The method includes bonding a first chip structure to the redistribution structure through the first conductive bump structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure extends across a first sidewall of the shield bump structure.

Abstract: A keyboard key device includes a keycap and a substrate unit. The substrate unit includes a light-emitting component, a light guide plate, and a light transmission plate. The light guide plate has first and second end surfaces, and at least one light-condensing hole. The first end surface is formed with an uneven microstructure for diffuse reflection of light rays. The light transmission plate has first and second side surfaces, and an outer reflective layer coated on the second side surface. A portion of light rays emitted from the light-emitting component and into the light transmission plate pass through the outer reflective layer, and the remainder of the light rays are reflected by the outer reflective layer.

Abstract: A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: A method for preparing optical fibers formed with high-particle-coated porous polymeric outer coating layer is provided. The method includes preparing a coating suspension solution by dispersing a plurality of particles into an organic solvent system, immersing one or more optical fibers into the coating suspension solution, removing the one or more optical fibers from the coating suspension solution to form high-particle-coated porous polymeric outer coating layer after drying. Concentrations and compositions of the particles in the coating suspension solution, concentrations and compositions of the organic solvent system, the period of time of immersing, or the external environment are adjusted such that the optical fibers is formed with high-particle-coated polymeric outer coating layers having desirable coating masses, coating thicknesses, or coating morphologies.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a package substrate, a first die, and a stiffener ring. The first die is disposed on the package substrate and has a first sidewall and a second sidewall opposite to each other. The stiffener ring is disposed on the package substrate to surround the first die. The stiffener ring has an inner sidewall facing the first die, and the inner sidewall at least has a slant sidewall facing the first sidewall of the first die.

Abstract: A microscope system (100) configured to record images in at least a first and a second imaging mode (501, 502), comprising: An objective (1) collecting light (201) from a sample (11), An illumination module coupled to the objective, A first reimaging objective (5) generating an intermediate image of the sample and a second reimaging objective (6) that relays the intermediate image onto a detection module, An evaluation module (200) comprising a machine learning method (DL), trained with a first and a second set of images of the same sample, wherein the first and second set has been acquired in the first (501) and second imaging mode (502), respectively, wherein upon acquisition of an image (400) in the second imaging mode (502) the trained machine learning method (DL) outputs a restored image (401) that comprises fewer aberrations than the image (400) acquired in the second imaging mode (52, 53, 57).

Abstract: A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar.